The Pulse

The Semiconductor IP Marketplace that puts you first

Semi IP Hub's mission is to provide you with a platform where you can find Silicon IP cores for your next project without being harassed by dozens of sellers.

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Spotlight

  • Post-Quantum ML-KEM IP Core
    • Efficient Performance
    • SCA/FIA Protections
    • Patented High-Performance Modulo Multiplication
    • Flexible Interfaces
  • MIPI SoundWire I3S Manager IP
    • The MIPI SoundWire I3S Manager IP enables efficient, low-power, and high-fidelity audio data transfer for mobile, consumer, and automotive applications.
    • Compliant with the MIPI SoundWire I3S (Inter-IC Sound) standards, it supports synchronized, multi-channel audio over a scalable two-wire interface, ideal for connecting digital microphones, amplifiers, and codecs in space-constrained designs.
    Block Diagram -- MIPI SoundWire I3S Manager IP
  • eDP 2.0 Verification IP
    • The eDP 2.0 Verification IP provides an effective & efficient way to verify the components interfacing with the eDP interface of an ASIC/FPGA or SoC.
    • The eDP VIP is fully compliant with the Standard eDP Version 2.0 specifications from VESA.
    • This VIP is a lightweight VIP with an easy plug-and-play interface, so that there is no hit on the design time and the simulation time.
    Block Diagram -- eDP 2.0 Verification IP
  • Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
    • Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex. Designed for a range of applications requiring maximum single thread performance in Linux-capable devices. Improved performance compared with Gen#1.
    Block Diagram -- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
  • LLM AI IP Core
    • For sophisticated workloads, DeepTransformCore is optimized for language and vision applications.
    • Supporting both encoder and decoder transformer architectures with flexible DRAM configurations and FPGA compatibility, DeepTransformCore eliminates complex software integration burdens, empowering customers to rapidly develop custom AI SoC (System-on-chip) designs with unprecedented efficiency.
    Block Diagram -- LLM AI IP Core
  • Post-Quantum Digital Signature IP Core
    • The KiviPQC-DSA is an IP core implementing the ML-DSA (Module-Lattice-based Digital Signature Algorithm) a post-quantum cryptographic standard defined by NIST FIPS 204.
    • Designed to withstand both classical and quantum computer attacks, ML-DSA ensures the authenticity and integrity of signed  data far into the future.
  • UCIe Die-to-Die Chiplet Controller
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    Block Diagram -- UCIe PHY & D2D Adapter
  • TSMC CLN5FF GUCIe LP Die-to-Die PHY
    Block Diagram -- TSMC CLN5FF GUCIe LP Die-to-Die PHY
  • PCIe 7.0 Controller with AXI
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
  • PCIe 7.0 PHY in TSMC (N5, N3P)
  • RISC-V CPU IP
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar
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