The Pulse

The Semiconductor IP Marketplace that puts you first

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Spotlight

  • SLM Signal Integrity Monitor
    • The SLM Signal Integrity Monitor (SIM) IP enables signal quality measurement for die-to-die interfaces. It can be implemented in silicon with minimal area overhead. It enables accurate measurement of silicon interconnects with real-time reporting for analytics.
    • With the use of Monitor, Test and Repair (MTR), this real-time reporting enables structural lane monitoring, aging related degradation, and optional repair of failing lanes to maintain high-speed performance throughout the silicon lifecycle.
    Block Diagram -- SLM Signal Integrity Monitor
  • Digital PUF IP
    • Generate unclonable 128 or 256-bit seeds with a compact, logic-based PUF that drops into any SoC.
    • Digital PUF IP adds true hardware identity for secure boot, key generation, and device authentication with minimal silicon overhead.
  • Embedded USB2 (eUSB) Controller + PHY IP
    • Compliant to Embedded USB2 Version2.0, Aug 2024
    • Supports high-speed, full-speed, and low-speed operation.
    • Meet low voltage requirement (1.0V – 1.2V)
    • No change in existing USB2/USB3 Port
    • Supports symmetric and asymmetric data rates
    Block Diagram -- Embedded USB2 (eUSB) Controller + PHY IP
  • SD4.x UHSII
    • Fully compliant with UHSII specification Ver. 4.x
    • Bidirectional receiver/transmitter (2 channels) supporting both full and half duplex modes
    • Supports data rates from 390Mbps to 1.56Gbps/ch
    • RCLK frequency: 26 to 56MHz
    • Built-in PLL and clock recovery
    Block Diagram -- SD4.x UHSII
  • 1.8V Capable GPIO on Samsung Foundry 4nm FinFET
    • The 1.8V capable GPIO is an IP macro for on-chip integration. It is a 1.8V general purpose I/O built with a stack of 1.2V MOS FINFET devices. It is controlled by 0.75V (core) signals.
    • Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
    Block Diagram -- 1.8V Capable GPIO on Samsung Foundry 4nm FinFET
  • Bluetooth Low Energy 6.0 Scalable RF IP
    • The SB1001 Scalable RF Transceiver IP is designed to maximise performance per μW across the full range of BLE applications, enabling receiver power consumption as low as 3mW for medical devices, whilst delivering up to +10dBm transmit power when needed for industrial applications.
    • It is optimised for applications such as BLE, 802.15.4 (Zigbee, Matter) and proprietary standards operating at 2.4GHz.
  • UCIe Die-to-Die Chiplet Controller
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    Block Diagram -- UCIe PHY & D2D Adapter
  • UCIe Die-to-Die PHY
    Block Diagram -- UCIe Die-to-Die PHY
  • PCIe 7.0 Controller with AXI
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
  • PCIe 7.0 PHY in TSMC (N5, N3P)
  • RISC-V CPU IP
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar
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