The Semiconductor IP Marketplace

Try an example: PCIe 7.0
☰ Semiconductor IP

The Pulse

The Semiconductor IP Marketplace that puts you first

Semi IP Hub's mission is to provide you with a platform where you can find Silicon IP cores for your next project without being harassed by dozens of sellers.

Here, your contact details are not shared with third parties unless you request to be contacted by a supplier.

Spotlight

  • 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
    • Fractional-N Phase locked loop frequency synthesizer is intended for ASIC clock generation.
    • The Fractional-N PLL loop with 2GHz-4GHz VCO has high phase noise performance and ultra-fine frequency tuning step.
    • VCO Sub-band auto select (SAS) system allows to find automatically appropriate sub-band for VCO on locked PLL.
    Block Diagram -- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
  • AGILEX 7 R-Tile Gen5 NVMe Host IP
    • The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD.
    • The register file interface simplify the management of the IP for CPU interface or State Machine interface using Avalon bus.
    Block Diagram -- AGILEX 7 R-Tile Gen5 NVMe Host IP
  • 100G PAM4 Serdes PHY - 14nm
    • The 100G SERDES PHY IP for VSR supports up to 100 Gbps data rate with low-power consumption and a small footprint.
    • It has advanced features such as equalization, and clock and data recovery, ensuring reliable data transmission.
    • The IP can be integrated into a variety of applications such as networking, data centers, and high-performance computing.
    Block Diagram -- 100G PAM4 Serdes PHY - 14nm
  • Bluetooth Low Energy Subsystem IP
    • The BLE v6.0 Subsystem IP consists of an integrated Controller and Modem paired to a  proprietary RF on T22 ULL.
    • It is ideally suited to ASIC developers or fabless semiconductor companies who want to add BLE functionality without the hassle of dealing with multiple IP vendors or design groups.​
    Block Diagram -- Bluetooth Low Energy Subsystem IP
  • Multi-core capable 64-bit RISC-V CPU with vector extensions
    • The SiFive® Intelligence™ X180 core IP products are designed to meet the increasing requirements of embedded IoT and AI at the far edge.
    • With this 64-bit version, X100 series IP delivers higher performance and better integration with larger memory systems.
    Block Diagram -- Multi-core capable 64-bit RISC-V CPU with vector extensions
  • EMFI Detector
    • The agileEMSensor is a Ring Oscillator (RO) based sensor designed to detect electromagnetic fault injection (EMFI) attacks on critical circuits.
    • It offers protection against Side-Channel Attacks (SCAs) and tampering through deliberate electromagnetic disturbances.
    • The sensor provides digital outputs to warn processors of intrusion attempts.

UCIe Controller IP View All

  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter

PCIe 7.0 IP View All

  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
  • PCIe 7.0 PHY in TSMC (N5, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SSC)

AI IP View All

  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar

MIPI IP View All

RISC-V IP View All

×
Semiconductor IP