The Pulse

The Semiconductor IP Marketplace that puts you first

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Spotlight

  • xSPI Multiple Bus Memory Controller
    • SLL’s unified xSPI Multiple Bus Memory Controller IP supports the widest range of JEDEC xSPI and xSPI-like NOR Flash and PSRAM memories (JEDEC xSPI Profile 1.0 and 2.0, HyperBus 1.0, 2.0 and 3.0, OctaBus and Xccela Bus) that are available now from many memory vendors.
    • JEDEC xSPI and xSPI-like memories offer good performance with lower hardware and power costs.  Memory device variants offer up to 512 Mbit PSRAM, up to 2 Gigabit NOR Flash, up to 250 MHz DDR clock speeds, with x4, x8 and x16 data path widths, and a wide range of package options including 4mm x 4mm BGA49 and tiny WLCSP footprints.  Some PRSAM devices are now also available with internal ECC.
    Block Diagram -- xSPI Multiple Bus Memory Controller
  • MIPI CSI-2 IP
    • The MIPI CSI-2 IP core is a highly scalable and silicon-agnostic implementation of the  MIPI Camera Serial Interface 2 version 4.1 targeting ASIC and FPGA technologies.
    • The MIPI CSI-2 implementation enables high-speed, low-power transmission of image data from camera modules to host processors.
    Block Diagram -- MIPI CSI-2 IP
  • PCIe Gen 7 Verification IP
    • The PCIe Gen 7 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 7 interface of an IP or SoC. 
    • The PCIe Gen 7 VIP is fully compliant with latest PCI Express Gen 7 specifications. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design cycle time.
    Block Diagram -- PCIe Gen 7 Verification IP
  • mmWave 8x8 MIMO RF Front End V2
    • Advanced mmWave 8x8 MIMO RF front-end silicon optimized for sophisticated wireless communication and beamforming.
    Block Diagram -- mmWave 8x8 MIMO RF Front End V2
  • CXL Controller IP
    • The CXL/PCIe Controller IP carries out CXL 3.0 specification and is backward compatible to CXL 2.0 and 1.1.
    • Possessing high customizability and supportability, this controller provides a comprehensive CXL solution.
    Block Diagram -- CXL Controller IP
  • PCIe Gen 6 Phy
    • Architecture optimized for HPC, AI/ML, storage, and networking
    • Ultra-long reach, low latency, and low power
    • Advanced DSP delivers unmatched performance and reliability
    • PCIe Gen 6 Phy IPPCIe Gen 6 Phy IPComprehensive real-time diagnostic, monitor, and test features
    Block Diagram -- PCIe Gen 6 Phy
  • UCIe Die-to-Die Chiplet Controller
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    Block Diagram -- UCIe PHY & D2D Adapter
  • 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
    Block Diagram -- 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
  • PCIe 7.0 Controller with AXI
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
  • PCIe 7.0 PHY in TSMC (N5, N3P)
  • RISC-V CPU IP
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar
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