The Pulse

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Spotlight

  • PSI5 IP Core Controller for Peripheral Sensor Interface 5 Communication
    • The DPSI5 is a hardware implementation of a controller for the Peripheral Sensor Interface (PSI5) protocol. This controller complies with the PSI5 protocol specification V2.3 and is designed for use in electronic control units (ECUs) to ensure communication with up to six sensors.
    • Data transmission from the sensor to the ECU is achieved through current modulation on the power supply line, with a data rate of 125 kbit/s or 189 kbit/s, using a Manchester decoder.
  • Quantum Safe, ISO 21434 Automotive-grade Programmable Hardware Security Module
    • The automotive-grade CryptoManager RT-7xx v3 Root of Trust family is the next generation of fully programmable ISO 26262 and ISO 21434 compliant hardware security modules offering Quantum Safe security by design for secure automotive applications.
    • The CryptoManager RT-7xx family protects against a wide range of hardware and software attacks through state-of-the-art side channel attack countermeasures and anti-tamper and security techniques.
    Block Diagram -- Quantum Safe, ISO 21434 Automotive-grade Programmable Hardware Security Module
  • Bluetooth 5.3 Dual Mode PHY IP
    • The icyTRX-DM ultra-low-power RF transceiver IP is designed to meet 2.4 GHz standards like Bluetooth Classic (BR/EDR), Bluetooth Low Energy (BLE), 802.15.4 PHY Layer (e.g. ZigBee), and proprietary standards.
    • icyTRX-DM IP targets by far the lowest power consumption together with state-of-the-art performances (sensitivity, interferers rejection) and with minimal cost.
    • Thanks to its built-in LDOs, its fully programmable modem and its interface compatible with leading BT baseband controllers, the icyTRX-DM IP is optimized for easy integration into ASICs and SoCs
    Block Diagram -- Bluetooth 5.3 Dual Mode PHY IP
  • IP library for the acceleration of edge AI/ML
    • A library with a wide selection of hardware IPs for the design of modular and flexible SoCs that enable end-to-end inference on miniaturized systems.
    • Available IP categories include ML accelerators, dedicated memory systems, the RISC-V based 32-bit processor core icyflex-V, and peripherals.
    Block Diagram -- IP library for the acceleration of edge AI/ML
  • 5G RAN DSP
    • The XC23 is the most powerful DSP core available today for communications applications. The-XC23 offers scalable architecture and dual thread design with support for AI, addressing growing demand for smarter, more efficient wireless infrastructure
    • Targeted for 5G and 5G-Advanced workloads, the XC23 has two independent execution threads and a dynamic scheduled vector-processor, providing not only unprecedented processing power but unprecedented utilization on real-world 5G multitasking workloads.
    Block Diagram -- 5G RAN DSP
  • High-efficiency, AI-based super resolution IP
    • The AI-SR series IPs offer super resolution solutions for enhancing video quality and pixel resolution, primarily used for post-processing or display applications.
    • Currently consisting of AISR1000 and AISR2000 IPs, this series enables generation or transfer of low-resolution sources for bandwidth reduction and performance improvement, while ensuring high-quality, high-resolution displays at the edge.
    Block Diagram -- High-efficiency, AI-based super resolution IP
  • UCIe Die-to-Die Chiplet Controller
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    Block Diagram -- UCIe PHY & D2D Adapter
  • 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
    Block Diagram -- 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
  • PCIe 7.0 Controller with AXI
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
  • PCIe 7.0 PHY in TSMC (N5, N3P)
  • RISC-V CPU IP
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar
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