The Semiconductor IP Marketplace

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Spotlight

  • HBM4 PHY IP
    • Supports JEDEC HBM4 DRAMs
    • Supports data rates up to 12 Gbps
    • Supports up to 32 independent 64-bit memory channels
    • Pseudo-channel operation supported to enable up to 64 32-bit pseudo-channels with 2048-bit PHY
  • 10-bit SAR ADC - XFAB XT018
    • The TS_ADC_10b_X8 is a 10-bit capacitive successive approximation register (SAR) Analog-to-Digital converter (ADC).
    • It operates with a 3.3 V analog power supply, a 1.8 V digital power supply, and an external voltage reference.
    • The ADC converts single-ended input voltages and requires no external S/H circuit.
    Block Diagram -- 10-bit SAR ADC - XFAB XT018
  • eFuse Controller IP
    • AMBA 3.0 APB interface for register access
    • Automated eFuse read, program, and reload operations
    • Protection against repeated programming of the same bits
    • Support for 32-bit aligned read/program operations
  • SDA OCT Encoder and Decoder
    • The SDA OCT Encoder handles the construction of Over-The-Air (OTA) frames as indicated in the standard, a preamble followed by a header and payload data, with both fields being protected by cyclic redundancy check (CRC) and forward error correction (FEC).
    • The SDA OCT Decoder performs the synchronization of the Over-The-Air (OTA) frame and then decodes the header and payload data within the frame. 
    Block Diagram -- SDA OCT Encoder and Decoder
  • Secure Storage Solution for OTP IP
    • Advanced Security: Encrypted storage in OTP using dynamic root key from SRAM PUF
    • System-Level Security Extension: Add-on allows sharing the SRAM PUF to protect chip-level assets
    • Flexible Security Configuration: Secure regions within OTP can be tailored to meet specific needs
    Block Diagram -- Secure Storage Solution for OTP IP
  • UDP Offload Engine for IPv6
    • Full IPv6 support including Echo, NDP, MLD
    • Line-rate UDP/IPv6 transmit and receive
    • RFC 768 & RFC 8200 compliant
    • Packet parsing and header synthesis in hardware

UCIe Controller IP View All

  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • TSMC CLN5FF GUCIe LP Die-to-Die PHY
    • IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
    • This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
    Block Diagram -- TSMC CLN5FF GUCIe LP Die-to-Die PHY

PCIe 7.0 IP View All

  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
  • PCIe 7.0 PHY in TSMC (N5, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SSC)

AI IP View All

  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar

MIPI IP View All

RISC-V IP View All

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