The Pulse
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Silvaco Strengthens Leadership Team with Three Industry Veterans to Drive Innovation and Growth
2025-07-24T14:05:00+00:00
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Beyond CNSA 2.0: The Expanding Horizon of Post-quantum Security
2025-07-24T07:40:00+00:00
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How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
2025-07-24T06:08:00+00:00
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JFE Shoji Electronics Signs Sales Agent Agreement with Andes Technology
2025-07-24T05:58:00+00:00
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SiFive Celebrates 10 Years as Your Trusted Partner for RISC-V IP Innovation
2025-07-23T15:21:00+00:00
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Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
2025-07-23T14:07:00+00:00
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Mixel Supports Automotive SerDes Alliance (ASA) Motion Link SerDes IP
2025-07-23T13:44:00+00:00
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Accelerating IP Reuse
2025-07-23T10:27:00+00:00
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Alphacore is gearing up for a high-impact presence at the 2025 Diminishing Manufacturing Sources and Material Shortages & Parts Management Consortium
2025-07-23T05:28:00+00:00
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SpaceX Acquires Akoustis’s IP, Murata and RadRock Dominate Q2 2025 RF Front-End Patent Activity
2025-07-23T04:54:00+00:00
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The TekStart Group Enters into Distribution Agreement with Techno Mathematical to Promote Advanced Hardware and Software CODEC Solutions
2025-07-22T14:20:00+00:00
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Alchip Introduces 2nm Design Platform
2025-07-22T14:08:00+00:00
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Arteris Selected by Whalechip for Near-Memory Computing Chip
2025-07-22T13:05:00+00:00
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Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions
2025-07-22T11:11:00+00:00
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Inside Cyient Semiconductors Bet on RISC-V for Custom Silicon
2025-07-22T10:38:00+00:00
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Faraday Delivers DDR/LPDDR Combo PHY IP Solutions on UMC's 22ULP and 14FFC
2025-07-22T08:42:00+00:00
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EnSilica cuts post-quantum cryptography (PQC) silicon area with three-in-one IP block
2025-07-21T11:26:00+00:00
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Perceptia Devices Release pPLL08W, best-in-class RF PLL IP in GF22FDX
2025-07-21T10:27:00+00:00
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How Mature-Technology ASICs Can Give You the Edge
2025-07-21T08:23:00+00:00
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Axiomise Partners With Bluespec to Verify Its RISC-V Cores
2025-07-20T18:43:00+00:00
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Rapidus Achieves Significant Milestone at its State-of-the-Art Foundry with Prototyping of Leading-Edge 2nm GAA Transistors
2025-07-20T05:31:00+00:00
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SEMIFIVE Files for Pre-IPO Review on KRX
2025-07-18T11:39:00+00:00
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MIPI: Powering the Future of Connected Devices
2025-07-18T06:12:00+00:00
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Innosilicon Scales LPDDR5X/5/4X/4 and DDR5/4 Combo IPs to 28nm and 22nm, Cementing Its Position as the ‘One Stop’ for Memory Interface Solutions
2025-07-18T04:15:00+00:00
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ESD Protection for an High Voltage Tolerant Driver Circuit in 4nm FinFET Technology
2025-07-17T14:56:00+00:00
The Semiconductor IP Marketplace that puts you first
Semi IP Hub's mission is to provide you with a platform where you can find Silicon IP cores for your next project without being harassed by dozens of sellers.
Here, your contact details are not shared with third parties unless you request to be contacted by a supplier.
Spotlight
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SLM Signal Integrity Monitor
- The SLM Signal Integrity Monitor (SIM) IP enables signal quality measurement for die-to-die interfaces. It can be implemented in silicon with minimal area overhead. It enables accurate measurement of silicon interconnects with real-time reporting for analytics.
- With the use of Monitor, Test and Repair (MTR), this real-time reporting enables structural lane monitoring, aging related degradation, and optional repair of failing lanes to maintain high-speed performance throughout the silicon lifecycle.
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Digital PUF IP
- Generate unclonable 128 or 256-bit seeds with a compact, logic-based PUF that drops into any SoC.
- Digital PUF IP adds true hardware identity for secure boot, key generation, and device authentication with minimal silicon overhead.
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Embedded USB2 (eUSB) Controller + PHY IP
- Compliant to Embedded USB2 Version2.0, Aug 2024
- Supports high-speed, full-speed, and low-speed operation.
- Meet low voltage requirement (1.0V – 1.2V)
- No change in existing USB2/USB3 Port
- Supports symmetric and asymmetric data rates
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SD4.x UHSII
- Fully compliant with UHSII specification Ver. 4.x
- Bidirectional receiver/transmitter (2 channels) supporting both full and half duplex modes
- Supports data rates from 390Mbps to 1.56Gbps/ch
- RCLK frequency: 26 to 56MHz
- Built-in PLL and clock recovery
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1.8V Capable GPIO on Samsung Foundry 4nm FinFET
- The 1.8V capable GPIO is an IP macro for on-chip integration. It is a 1.8V general purpose I/O built with a stack of 1.2V MOS FINFET devices. It is controlled by 0.75V (core) signals.
- Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
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Bluetooth Low Energy 6.0 Scalable RF IP
- The SB1001 Scalable RF Transceiver IP is designed to maximise performance per μW across the full range of BLE applications, enabling receiver power consumption as low as 3mW for medical devices, whilst delivering up to +10dBm transmit power when needed for industrial applications.
- It is optimised for applications such as BLE, 802.15.4 (Zigbee, Matter) and proprietary standards operating at 2.4GHz.
UCIe Controller IP View All
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UCIe Die-to-Die Chiplet Controller
- High configurability and customizability
- Defines packets to communicate with a link partner using different AXI parameters
- Supports raw streaming modes
- Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
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UCIe PHY & D2D Adapter
- 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
- UCIe v1.1 specification
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UCIe Die-to-Die PHY
- High Bandwidth Density and Data Rates
- Package Configurability
- Energy Efficiency
- Fully Integrated Solution
PCIe 7.0 IP View All
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PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/completion traffic
- Handles up to 4 TLPs per cycle
- Advanced PIPE modes and port bifurcation
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PCIe 7.0 PHY IP
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
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PCIe 7.0 PHY in TSMC (N5, N3P)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SSC)
AI IP View All
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RISC-V CPU IP
- RISC-V RVA23 Compliant
- >18 SPECint2006/GHz
- 8-wide decode unit
- Advanced branch predictor
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NPU IP for Embedded ML
- Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
- Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
- Future proof architecture that supports the most advanced ML data types and operators
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Future-proof IP for training and inference with leading performance per watt and per dollar
- RISC-V-based AI IP development for enhanced training and inference.
- Silicon-proven solutions tailored for AI workload optimization.
- Energy-efficient performance with industry-leading Perf/W.
MIPI IP View All
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
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MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
RISC-V IP View All
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32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32/64 Bit RISC-V core
- 5-stage pipeline
- In-order, Single issue
- Multicore Capable (up to 8 cores)
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Dual-issue Linux-capable RISC-V core
- 64-bit RISC-V core
- RVA22 profile
- Linux capable
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High-performance RISC-V CPU
- Fully compliant with the RVA23 RISC-V specification
- Comparable PPA to Arm Neoverse V3 / Cortex-X4
- Standard AMBA CHI.E coherent interface for SoC and chiplet integration
- Co-architected with Veyron E2 for seamless vector, AI acceleration, and big-little style heterogeneous compute configurations