The Semiconductor IP Marketplace

Spotlight

• 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm

  • A Flipchip I/O Library with dynamitcally switchable 1.8V/3.3V GPIO, 5V I2C/SM- Bus ODIO, 5V OTP Cell, 1.8V & 3.3V Analog Cells and associated ESD.
  • A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
  
• 5G IoT DSP

  • The XC21 is the most efficient vector DSP core available today for communications applications.
  • The XC21 DSP is designed for low-power, cost- and size-optimized cellular IoT modems, NTN VSAT terminals, eMBB and uRLLC applications.
  • Ceva-XC21 offers scalable architecture and dual thread design with support for AI, addressing growing demand for smarter, yet more cost and power efficient cellular devices
  
• PCIe GEN6 PHY IP

  • The PCIe GEN6 PHY IP achieves data rates up to 64GT/s per lane with PAM4 signaling thereby delivering reliable performance for high-speed data transfer.
  • It supports advanced applications, including AI/ML, High-Performance Computing, and next-generation storage solutions.
  
• PSI5 IP Core Controller for Peripheral Sensor Interface 5 Communication

  • The DPSI5 is a hardware implementation of a controller for the Peripheral Sensor Interface (PSI5) protocol. This controller complies with the PSI5 protocol specification V2.3 and is designed for use in electronic control units (ECUs) to ensure communication with up to six sensors.
  • Data transmission from the sensor to the ECU is achieved through current modulation on the power supply line, with a data rate of 125 kbit/s or 189 kbit/s, using a Manchester decoder.
• Quantum Safe, ISO 21434 Automotive-grade Programmable Hardware Security Module

  • The automotive-grade CryptoManager RT-7xx v3 Root of Trust family is the next generation of fully programmable ISO 26262 and ISO 21434 compliant hardware security modules offering Quantum Safe security by design for secure automotive applications.
  • The CryptoManager RT-7xx family protects against a wide range of hardware and software attacks through state-of-the-art side channel attack countermeasures and anti-tamper and security techniques.
  
• Bluetooth 5.3 Dual Mode PHY IP

  • The icyTRX-DM ultra-low-power RF transceiver IP is designed to meet 2.4 GHz standards like Bluetooth Classic (BR/EDR), Bluetooth Low Energy (BLE), 802.15.4 PHY Layer (e.g. ZigBee), and proprietary standards.
  • icyTRX-DM IP targets by far the lowest power consumption together with state-of-the-art performances (sensitivity, interferers rejection) and with minimal cost.
  • Thanks to its built-in LDOs, its fully programmable modem and its interface compatible with leading BT baseband controllers, the icyTRX-DM IP is optimized for easy integration into ASICs and SoCs
  

UCIe Controller IP View All

• UCIe Die-to-Die Chiplet Controller

  • High configurability and customizability
  • Defines packets to communicate with a link partner using different AXI parameters
  • Supports raw streaming modes
  • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
  
• UCIe PHY & D2D Adapter

  • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
  • UCIe v1.1 specification
  
• 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe

  • High Bandwidth Density and Data Rates
  • Package Configurability
  • Energy Efficiency
  • Fully Integrated Solution
  

PCIe 7.0 IP View All

• PCIe 7.0 Controller with AXI

  • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
  • Separate native TX/RX data path separating posted/Non posted/completion traffic
  • Handles up to 4 TLPs per cycle
  • Advanced PIPE modes and port bifurcation
  
• PCIe 7.0 PHY IP

  • Physical Coding Sublayer (PCS) block with PIPE interface
  • Supports PCIe 7.0, encoding, backchannel initialization
  • Lane margining at the receiver
• PCIe 7.0 PHY in TSMC (N5, N3P)

  • Physical Coding Sublayer (PCS) block with PIPE interface
  • Supports PCIe 7.0, encoding, backchannel initialization
  • Lane margining at the receiver
  • Spread-spectrum clocking (SSC)

AI IP View All

• RISC-V CPU IP

  • RISC-V RVA23 Compliant 
  • >18 SPECint2006/GHz
  • 8-wide decode unit
  • Advanced branch predictor
  
• NPU IP for Embedded ML

  • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
  • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
  • Future proof architecture that supports the most advanced ML data types and operators
  
• Future-proof IP for training and inference with leading performance per watt and per dollar

  • RISC-V-based AI IP development for enhanced training and inference.
  • Silicon-proven solutions tailored for AI workload optimization.
  • Energy-efficient performance with industry-leading Perf/W.
  

MIPI IP View All

• MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6

  • Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
  • Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
  
• MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.

  • Fully compliant to MIPI standard
  • Small footprint
  • Code validated with Spyglass
  
• MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)

  • Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
  • Supports standard PHY transceiver compliant to MIPI Specification
  • Supports standard PPI interface compliant to MIPI Specification
  • Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
  

RISC-V IP View All

• 32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.

  • 32/64 Bit RISC-V core
  • 5-stage pipeline
  • In-order, Single issue
  • Multicore Capable (up to 8 cores)
  
• Dual-issue Linux-capable RISC-V core

  • 64-bit RISC-V core
  • RVA22 profile
  • Linux capable
  
• RISC-V high performance CPU

  • Aggressive eight-wide deep out-of-order pipeline
  • Unique 512KB IL2(I-cache) with DL1/DL2 (512KB) split vs unified 1MB L2