The Semiconductor IP Marketplace
Spotlight
-
HBM4 Memory Controller
- Supports HBM4 memory devices
- Supports all standard HBM4 channel densities (up to 32 Gb)
- Supports up to 10 Gbps/pin
- Refresh Management (RFM) support
-
Ultra Low Power AI core
- Ultra-low power standalone NPU core (<1mW)
- Support power islands for minimal standby power
- Industry-standard development environment
-
Controller for MIPI Soundwire
- MIPI compliant peripheral controller with multi-lane capability
- APB Peripheral interface for control port and manager configuration registers
- APB Initiator interface for external user defined registers
-
-
UCIe Die-to-Die Chiplet Controller
- High configurability and customizability
- Defines packets to communicate with a link partner using different AXI parameters
- Supports raw streaming modes
- Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
-
-
-
PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Scalable data path
- Advanced PIPE modes and port bifurcation
- Supports multiple virtual channels (VCs) in FLIT and non-FLIT modes
-
PCIe 7.0 PHY IP
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
-
PCIe 7.0 PHY in TSMC (N5, N3P)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SSC)
-
NPU IP for Embedded AI
- Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
- Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
- Future proof architecture that supports the most advanced ML data types and operators
-
-
-
-
-
MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
-
-
-
RISC-V high performance CPU
- Aggressive eight-wide deep out-of-order pipeline
- Unique 512KB IL2(I-cache) with DL1/DL2 (512KB) split vs unified 1MB L2