The Pulse
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Premier ASIC and SoC Design Partner, Sondrel, Rebrands as Aion Silicon
2025-04-25T19:28:00+02:00
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Intel Financial Risks, Layoffs, Foundry Ambitions
2025-04-25T15:41:00+02:00
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BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
2025-04-25T14:53:00+02:00
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The Growing Importance of PVT Monitoring for Silicon Lifecycle Management
2025-04-25T13:43:00+02:00
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China Takes the Lead in RF Front-End Patent Activity: RadRock and Others Surge Behind Murata
2025-04-25T13:21:00+02:00
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Arteris Wins Two Gold and One Silver Stevie® Awards in the 2025 American Business Awards®
2025-04-25T08:14:00+02:00
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Baya Systems, Imagination Technologies and Andes Technology to Present on Heterogeneous Compute Architectures at Andes RISC-V CON Silicon Valley
2025-04-24T21:36:00+02:00
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Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
2025-04-24T21:27:00+02:00
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Crypto Quantique announces QRoot Lite – a lightweight and configurable root-of-trust IP for resource-constrained IoT devices
2025-04-24T18:07:00+02:00
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Xylon Introduces Xylon ISP Studio
2025-04-24T16:47:00+02:00
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Alphawave Semi: Q1 2025 Trading and Business Update
2025-04-24T14:38:00+02:00
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Faraday Adds QuickLogic eFPGA to FlashKit‑22RRAM SoC for IoT Edge
2025-04-24T14:28:00+02:00
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Debugging Complex Multicore Microcontroller Applications
2025-04-24T13:54:00+02:00
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M31 Collaborates with TSMC to Advance 2nm eUSB2 IP Innovation
2025-04-24T12:52:00+02:00
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Crypto Quantique publishes independent cetome analysis on streamlining CRA compliance with the QuarkLink security platform
2025-04-24T10:33:00+02:00
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PQShield launches UltraPQ-Suite for deeply specialized implementations of post-quantum cryptography
2025-04-24T10:04:00+02:00
The Semiconductor IP Marketplace that puts you first
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Spotlight
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xSPI Multiple Bus Memory Controller
- SLL’s unified xSPI Multiple Bus Memory Controller IP supports the widest range of JEDEC xSPI and xSPI-like NOR Flash and PSRAM memories (JEDEC xSPI Profile 1.0 and 2.0, HyperBus 1.0, 2.0 and 3.0, OctaBus and Xccela Bus) that are available now from many memory vendors.
- JEDEC xSPI and xSPI-like memories offer good performance with lower hardware and power costs. Memory device variants offer up to 512 Mbit PSRAM, up to 2 Gigabit NOR Flash, up to 250 MHz DDR clock speeds, with x4, x8 and x16 data path widths, and a wide range of package options including 4mm x 4mm BGA49 and tiny WLCSP footprints. Some PRSAM devices are now also available with internal ECC.
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MIPI CSI-2 IP
- The MIPI CSI-2 IP core is a highly scalable and silicon-agnostic implementation of the MIPI Camera Serial Interface 2 version 4.1 targeting ASIC and FPGA technologies.
- The MIPI CSI-2 implementation enables high-speed, low-power transmission of image data from camera modules to host processors.
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PCIe Gen 7 Verification IP
- The PCIe Gen 7 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 7 interface of an IP or SoC.
- The PCIe Gen 7 VIP is fully compliant with latest PCI Express Gen 7 specifications. This VIP is a light weight with an easy plug-and-play interface so that there is no hit on the design cycle time.
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mmWave 8x8 MIMO RF Front End V2
- Advanced mmWave 8x8 MIMO RF front-end silicon optimized for sophisticated wireless communication and beamforming.
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CXL Controller IP
- The CXL/PCIe Controller IP carries out CXL 3.0 specification and is backward compatible to CXL 2.0 and 1.1.
- Possessing high customizability and supportability, this controller provides a comprehensive CXL solution.
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PCIe Gen 6 Phy
- Architecture optimized for HPC, AI/ML, storage, and networking
- Ultra-long reach, low latency, and low power
- Advanced DSP delivers unmatched performance and reliability
- PCIe Gen 6 Phy IPPCIe Gen 6 Phy IPComprehensive real-time diagnostic, monitor, and test features
UCIe Controller IP View All
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UCIe Die-to-Die Chiplet Controller
- High configurability and customizability
- Defines packets to communicate with a link partner using different AXI parameters
- Supports raw streaming modes
- Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
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UCIe PHY & D2D Adapter
- 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
- UCIe v1.1 specification
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2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- High Bandwidth Density and Data Rates
- Package Configurability
- Energy Efficiency
- Fully Integrated Solution
PCIe 7.0 IP View All
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PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/completion traffic
- Handles up to 4 TLPs per cycle
- Advanced PIPE modes and port bifurcation
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PCIe 7.0 PHY IP
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
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PCIe 7.0 PHY in TSMC (N5, N3P)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SSC)
AI IP View All
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RISC-V CPU IP
- RISC-V RVA23 Compliant
- >18 SPECint2006/GHz
- 8-wide decode unit
- Advanced branch predictor
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NPU IP for Embedded ML
- Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
- Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
- Future proof architecture that supports the most advanced ML data types and operators
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Future-proof IP for training and inference with leading performance per watt and per dollar
- RISC-V-based AI IP development for enhanced training and inference.
- Silicon-proven solutions tailored for AI workload optimization.
- Energy-efficient performance with industry-leading Perf/W.
MIPI IP View All
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
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MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
RISC-V IP View All
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32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32/64 Bit RISC-V core
- 5-stage pipeline
- In-order, Single issue
- Multicore Capable (up to 8 cores)
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Dual-issue Linux-capable RISC-V core
- 64-bit RISC-V core
- RVA22 profile
- Linux capable
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RISC-V high performance CPU
- Aggressive eight-wide deep out-of-order pipeline
- Unique 512KB IL2(I-cache) with DL1/DL2 (512KB) split vs unified 1MB L2