The Pulse

The Semiconductor IP Marketplace that puts you first

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Spotlight

  • Simulation VIP for AMBA CHI-C2C
    • Incorporating the latest protocol updates, the Cadence Verification IP for CHI-C2C provides a complete bus functional model (BFM), integrated automatic protocol checks, and a coverage model.
    • Designed for easy integration in testbenches at IP, systems with multiple CPUs, accelerators, or other device chiplets, the VIP for CHI-C2C provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms.
    Block Diagram -- Simulation VIP for AMBA CHI-C2C
  • Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
    • 003TSMC_PVT_01 IP library is a unique solution intended to continuously monitor IC status at several on-die locations.
    • It is able to detect manufacturing process deviation, perform voltage, current and die temperature measurement.  
    Block Diagram -- Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V)  -  TSMC 3nm N3P
  • USB 20Gbps Device Controller
    • Leveraging the benefits of USB 10Gbps and 5Gbps device controller, USB 20Gbps is designed using the FPGA built-in transceiver.
    • It is a one-stop solution for all USB requirements ranging from USB 3.2 to USB 2.0.
    • It supports SuperSpeed+ (SSP x2/x1), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes.
    Block Diagram -- USB 20Gbps Device Controller
  • SM4 Cipher Engine
    • The SM4 IP core implements a custom hardware accelerator for the SM4 symmetric block cipher, specified in Chinese national standard GB/T 32907-2016, and ISO/IEC 18033-3:2010/Amd 1:2021.
    • Designed for easy integration, the core, internally expanding the 128-bit key, is capable of both encryption and decryption and features a simple handshake input and output data interface.
    Block Diagram -- SM4 Cipher Engine
  • Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
    • The ODT-ADS-7B64G-3 is an ultra-high-bandwidth time-interleaved ADC designed in a 3nm CMOS process.
    • This 7-bit, 64GSPS ADC supports ac-coupled input signals up to Nyquist and features a full-scale range of 0.45Vpp differential, excellent dynamic performance, and low noise operation.
    Block Diagram -- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC	on 3nm
  • Fault Tolerant DDR2/DDR3/DDR4 Memory controller
    • FTADDR is a memory controller for DDR2,DDR3 and DDR4 SDRAM memory devices.
    • It uses a strong error correction code to achieve exceptional fault tolerance
    Block Diagram -- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
  • UCIe Die-to-Die Chiplet Controller
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    Block Diagram -- UCIe PHY & D2D Adapter
  • PCIe 7.0 Controller with AXI
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
  • PCIe 7.0 PHY in TSMC (N5, N3P)
  • RISC-V CPU IP
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar
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