The Semiconductor IP Marketplace

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Spotlight

  • Parallel Processing Unit
    • The Parallel Processing Unit (PPU) is an IP block that integrates tightly with the CPU on the same silicon.
    • It is designed to be highly configurable to specific meet requirements of numerous use cases. 
    Block Diagram -- Parallel Processing Unit
  • High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X
    • The HBM3 IP consists of a PHY and memory controller optimized for Samsung SF4X process to support the HBM3 memory standard (JESD238A) operating at up to 9.6 Gbps/pin.
    • The HBM3 IP is designed for high memory throughput and low latency applications while minimizing area and power consumption.
    Block Diagram -- High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X
  • Crystal Oscillators
    • The crystal oscillator macros are available in a wide range of industry-standard quartz crystals and MEMS resonators operating in the fundamental mode in the 32 kHz to 80 MHz range.
    • These oscillators, which are both power and area efficient, have a programmable transconductance to allow users to find the optimal balance between jitter and power consumption.
    Block Diagram -- Crystal Oscillators
  • SENT/SAE J2716 Receiver
    • The CSENT-RX core implements a receiver for the Single Edge Nibble Transmission (SENT) protocol.
    • It complies with the SAE J2716 standard and supports both synchronous and asynchronous sensors.
    • It can be used for receiving data from one or multiple sensors using a single SENT line.
    Block Diagram -- SENT/SAE J2716 Receiver
  • LLM Accelerator IP for Multimodal, Agentic Intelligence
    • HyperThought is a cutting-edge LLM accelerator IP designed to revolutionize AI applications.
    • Built for the demands of multimodal and agentic intelligence, HyperThought delivers unparalleled performance, efficiency, and security.
    Block Diagram -- LLM Accelerator IP for Multimodal, Agentic Intelligence
  • ORAN IP core
    • ORAN IP core is a highly scalable and silicon agnostic implementation of the interoperable O-RAN WG4 defined 7.2x interface for deployment in O-DU and O-RU products, targeting any ASIC, FPGA or ASSP technologies.
    • The ORAN over eCPRI implementation builds on long-time experience designing CPRI and Radio-Over-Ethernet solutions for fronthaul and delivers a flexible engine that is prepared for tight integration with software applications.
    Block Diagram -- ORAN IP core

UCIe Controller IP View All

  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe

PCIe 7.0 IP View All

  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
  • PCIe 7.0 PHY in TSMC (N5, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SSC)

AI IP View All

  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar

MIPI IP View All

RISC-V IP View All

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