The Semiconductor IP Marketplace

Try an example: PCIe 7.0

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Spotlight

  • Fixed Point Doppler Channel IP core
    • Support for orbital heights (h) in the range from 200 to 2000 km
    • Support for carrier frequencies ( fc) in the range from 137 to 2200 MHz
    • Support for sample frequencies ( fs) in the range from 500 Ksps to 500 Gsps
    • Support variations in the initial elevation angle due to different latitudes, obstructions in the visibility region, and regulatory requirements
  • Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
    • Full Bluetooth dual mode (Classic and LE) support, including next generation High Data Throughput up to 7.5Mbps for lossless multichannel low latency audio streaming.
    • IEEE 802.15.4 support, for Zigbee, Thread and Matter
    • Comprehensive Integration: Includes RF, modem, controller, software stacks, and profiles.
    • Advanced Audio Support: Supports Classic Audio, LE Audio, and Auracast Broadcast Audio.
  • Polyphase Video Scaler
    • High quality polyphase algorithm
    • High resolution support from 240×240 to 4k
    • Processing up to 4k@60 fps
    • Features dynamic resizing built-in anti-aliasing
    Block Diagram -- Polyphase Video Scaler
  • MIPI D-PHY Universal IP in UMC 28HPC+
    • Supports MIPI Alliance Specification for D-PHY Version 2.5
    • Consists of 1 Clock lane and 4 Data lanes
    • Embedded, high performance, and highly programmable PLL
    • Supports both low-power mode and high speed mode with integrated SERDES
    Block Diagram -- MIPI D-PHY Universal IP in UMC 28HPC+

UCIe Controller IP View All

PCIe 7.0 IP View All

  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Scalable data path
    • Advanced PIPE modes and port bifurcation
    • Supports multiple virtual channels (VCs) in FLIT and non-FLIT modes
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
  • PCIe 7.0 PHY in TSMC (N5, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SSC)

AI IP View All

  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded AI
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded AI
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar

MIPI IP View All

RISC-V IP View All

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