The Pulse
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NXP Completes Acquisitions of Aviva Links and Kinara to Advance Automotive Connectivity and AI at the Intelligent Edge
2025-10-30T16:25:49+00:00
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RISC-V Summit spurs new round of automotive support
2025-10-30T16:20:31+00:00
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xMEMS Raises $21M Series D to Accelerate Commercial Scale of Breakthrough piezoMEMS Technologies for AI-Enabled Consumer Devices
2025-10-30T14:55:39+00:00
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PQShield and Carahsoft Partner to Make Powerful Post-Quantum Cryptography Solutions Available to Government Agencies
2025-10-30T14:44:45+00:00
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GlobalFoundries and Silicon Labs Expand Partnership to Accelerate Wireless Connectivity Solutions and Strengthen U.S. Chip Manufacturing
2025-10-30T14:30:15+00:00
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Credo Announces Changes to Board, Appointing Brian Kelleher, Former Senior Vice President of Engineering with NVIDIA, to Independent Director Role
2025-10-30T13:29:09+00:00
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TASKING and LDRA Announce Advanced Data and Control Coupling Capabilities to Measure Hidden Timing Interference in Multi-core Applications
2025-10-30T12:13:35+00:00
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Alphacore Delighted to Announce it Achieved ISO 9001:2015 Certification – Received June 24, 2025
2025-10-30T07:03:00+00:00
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Rambus Reports Third Quarter 2025 Financial Results
2025-10-29T14:26:41+00:00
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ML-KEM explained: Quantum-safe Key Exchange for secure embedded Hardware
2025-10-29T12:35:18+00:00
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Attack on a PUF-based Secure Binary Neural Network
2025-10-29T09:40:00+00:00
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High Performance RISC-V is here!
2025-10-29T07:31:00+00:00
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Synopsys Spotlights Agentic AI, Accelerated Computing, and AI Physics at NVIDIA GTC Washington, D.C.
2025-10-29T07:10:25+00:00
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Quintauris and HighTec EDV Systeme Join Forces to Advance RISC-V Ecosystem for Automotive
2025-10-29T07:00:41+00:00
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GlobalFoundries Plans Billion-Euro Investment to Expand Chip Manufacturing in Germany
2025-10-29T06:50:00+00:00
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Rivos Collaborates to Complete Secure Provisioning of Integrated OpenTitan Root of Trust During SoC Production
2025-10-28T14:32:00+00:00
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Ceva and embedUR systems Partner to Launch ModelNova for NeuPro NPU Family, Expanding Edge AI Model Ecosystem
2025-10-28T12:02:00+00:00
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BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement
2025-10-28T11:14:39+00:00
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Faraday Reports Third Quarter 2025 Results
2025-10-28T10:37:19+00:00
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FD-SOI: A Cyber-Resilient Substrate Against Laser Fault Injection—The Future Platform for Secure Automotive Electronics
2025-10-28T09:57:00+00:00
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European high-performance energy-efficient processors for supercomputing, AI and data centres - Status and Roadmap
2025-10-28T08:50:00+00:00
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Is LLM Useful for Automotive Applications?
2025-10-28T07:10:29+00:00
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POLYN Technology Announces First Silicon-Implemented NASP™ Chip
2025-10-28T06:50:22+00:00
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FortifyIQ Secures the Quantum Era with Over-the-Air Updatable Cryptography
2025-10-27T20:56:00+00:00
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Cadence Reports Third Quarter 2025 Financial Results
2025-10-27T20:47:39+00:00
The Semiconductor IP Marketplace that puts you first
Semi IP Hub's mission is to provide you with a platform where you can find Silicon IP cores for your next project without being harassed by dozens of sellers.
Here, your contact details are not shared with third parties unless you request to be contacted by a supplier.
Spotlight
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Post-Quantum ML-KEM IP Core
- Efficient Performance
- SCA/FIA Protections
- Patented High-Performance Modulo Multiplication
- Flexible Interfaces
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MIPI SoundWire I3S Manager IP
- The MIPI SoundWire I3S Manager IP enables efficient, low-power, and high-fidelity audio data transfer for mobile, consumer, and automotive applications.
- Compliant with the MIPI SoundWire I3S (Inter-IC Sound) standards, it supports synchronized, multi-channel audio over a scalable two-wire interface, ideal for connecting digital microphones, amplifiers, and codecs in space-constrained designs.
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eDP 2.0 Verification IP
- The eDP 2.0 Verification IP provides an effective & efficient way to verify the components interfacing with the eDP interface of an ASIC/FPGA or SoC.
- The eDP VIP is fully compliant with the Standard eDP Version 2.0 specifications from VESA.
- This VIP is a lightweight VIP with an easy plug-and-play interface, so that there is no hit on the design time and the simulation time.
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Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex. Designed for a range of applications requiring maximum single thread performance in Linux-capable devices. Improved performance compared with Gen#1.
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LLM AI IP Core
- For sophisticated workloads, DeepTransformCore is optimized for language and vision applications.
- Supporting both encoder and decoder transformer architectures with flexible DRAM configurations and FPGA compatibility, DeepTransformCore eliminates complex software integration burdens, empowering customers to rapidly develop custom AI SoC (System-on-chip) designs with unprecedented efficiency.
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Post-Quantum Digital Signature IP Core
- The KiviPQC-DSA is an IP core implementing the ML-DSA (Module-Lattice-based Digital Signature Algorithm) a post-quantum cryptographic standard defined by NIST FIPS 204.
- Designed to withstand both classical and quantum computer attacks, ML-DSA ensures the authenticity and integrity of signed data far into the future.
UCIe Controller IP View All
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UCIe Die-to-Die Chiplet Controller
- High configurability and customizability
- Defines packets to communicate with a link partner using different AXI parameters
- Supports raw streaming modes
- Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
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UCIe PHY & D2D Adapter
- 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
- UCIe v1.1 specification
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TSMC CLN5FF GUCIe LP Die-to-Die PHY
- IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
- This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
PCIe 7.0 IP View All
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PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/completion traffic
- Handles up to 4 TLPs per cycle
- Advanced PIPE modes and port bifurcation
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PCIe 7.0 PHY IP
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
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PCIe 7.0 PHY in TSMC (N5, N3P)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SSC)
AI IP View All
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RISC-V CPU IP
- RISC-V RVA23 Compliant
- >18 SPECint2006/GHz
- 8-wide decode unit
- Advanced branch predictor
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NPU IP for Embedded ML
- Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
- Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
- Future proof architecture that supports the most advanced ML data types and operators
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Future-proof IP for training and inference with leading performance per watt and per dollar
- RISC-V-based AI IP development for enhanced training and inference.
- Silicon-proven solutions tailored for AI workload optimization.
- Energy-efficient performance with industry-leading Perf/W.
MIPI IP View All
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
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MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
RISC-V IP View All
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32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32/64 Bit RISC-V core
- 5-stage pipeline
- In-order, Single issue
- Multicore Capable (up to 8 cores)
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Dual-issue Linux-capable RISC-V core
- 64-bit RISC-V core
- RVA22 profile
- Linux capable
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High-performance RISC-V CPU
- Fully compliant with the RVA23 RISC-V specification
- Comparable PPA to Arm Neoverse V3 / Cortex-X4
- Standard AMBA CHI.E coherent interface for SoC and chiplet integration
- Co-architected with Veyron E2 for seamless vector, AI acceleration, and big-little style heterogeneous compute configurations