The Pulse
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Qualcomm to Acquire Arduino—Accelerating Developers’ Access to its Leading Edge Computing and AI
2025-10-07T18:48:00+00:00
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Accelerate Automotive System Design with Cadence AI-Driven DSPs
2025-10-07T14:12:00+00:00
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Quintauris and Lauterbach Elevate RISC-V Debug & Trace Capabilities for Automotive
2025-10-07T13:21:00+00:00
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Omni Design Technologies Tapes Out Ultra-High-Speed 64GSPS ADC on TSMC N3 process
2025-10-07T13:10:00+00:00
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IntoPIX Accelerates Automotive Innovation With TicoRAW & JPEG XS On Lattice Low Power FPGAs
2025-10-07T12:28:00+00:00
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What Makes FPGA Architecture Ideal for Ultra-Low-Latency Systems?
2025-10-07T12:18:00+00:00
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GUC Monthly Sales Report – September 2025
2025-10-07T12:07:00+00:00
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Introducing agileSecure anti-tamper security portfolio
2025-10-07T11:46:00+00:00
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ASIC North Enters Strategic Channel Partnership with GlobalFoundries
2025-10-07T11:40:00+00:00
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Same Chip, Two Destinies: How Power Profiles Improve With On-Chip Monitoring
2025-10-07T08:22:00+00:00
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UMC Reports Sales for September 2025
2025-10-07T08:04:00+00:00
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UCIe™ Chiplet IP on TSMC 3DFabric® Platform
2025-10-07T07:55:00+00:00
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UFS 5.0 Is Coming: JEDEC® Sets the Stage for the Next Leap in Flash Storage
2025-10-06T15:04:00+00:00
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ESD Alliance Reports Electronic System Design Industry Posts $5.1 Billion in Revenue in Q2 2025
2025-10-06T14:04:00+00:00
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Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage
2025-10-06T13:04:00+00:00
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A Hybrid Subsystem Architecture to Elevate Edge AI
2025-10-06T12:30:00+00:00
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IntoPIX Launches Codec Plugin Pack For JPEG XS - FastTicoXS Now In GStreamer
2025-10-06T11:43:00+00:00
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Multiple ways JESD204 performs bitstream alignment
2025-10-06T11:41:00+00:00
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PAM4 and Coherent-lite Interconnect for Hyperscale Campuses and AI Data Centers
2025-10-06T11:28:00+00:00
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Key Asic Berhad Signs RM1.11 Million Contract to Jointly Develop AI-Driven, Ultra-Low Power RF Navigation Chip with Middle East Partner
2025-10-06T11:14:00+00:00
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Accelerating AI Workloads with NVMe® over Fabrics (NVMe-oF™) Technology
2025-10-06T10:56:00+00:00
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Andes Technology Expands Comprehensive AndeSentry™ Security Suite with Complete Trusted Execution Environment Support for Embedded Systems
2025-10-06T07:19:00+00:00
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A Resource-Driven Approach for Implementing CNNs on FPGAs Using Adaptive IPs
2025-10-06T06:37:00+00:00
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Global Semiconductor Sales Increase 21.7% Year-to-Year in August
2025-10-06T05:57:00+00:00
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Weebit Nano tapes out embedded ReRAM test chips at onsemi production fab
2025-10-06T05:51:00+00:00
The Semiconductor IP Marketplace that puts you first
Semi IP Hub's mission is to provide you with a platform where you can find Silicon IP cores for your next project without being harassed by dozens of sellers.
Here, your contact details are not shared with third parties unless you request to be contacted by a supplier.
Spotlight
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Simulation VIP for AMBA CHI-C2C
- Incorporating the latest protocol updates, the Cadence Verification IP for CHI-C2C provides a complete bus functional model (BFM), integrated automatic protocol checks, and a coverage model.
- Designed for easy integration in testbenches at IP, systems with multiple CPUs, accelerators, or other device chiplets, the VIP for CHI-C2C provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms.
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Process/Voltage/Temperature Sensor with Self-calibration (Supply voltage 1.2V) - TSMC 3nm N3P
- 003TSMC_PVT_01 IP library is a unique solution intended to continuously monitor IC status at several on-die locations.
- It is able to detect manufacturing process deviation, perform voltage, current and die temperature measurement.
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USB 20Gbps Device Controller
- Leveraging the benefits of USB 10Gbps and 5Gbps device controller, USB 20Gbps is designed using the FPGA built-in transceiver.
- It is a one-stop solution for all USB requirements ranging from USB 3.2 to USB 2.0.
- It supports SuperSpeed+ (SSP x2/x1), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes.
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SM4 Cipher Engine
- The SM4 IP core implements a custom hardware accelerator for the SM4 symmetric block cipher, specified in Chinese national standard GB/T 32907-2016, and ISO/IEC 18033-3:2010/Amd 1:2021.
- Designed for easy integration, the core, internally expanding the 128-bit key, is capable of both encryption and decryption and features a simple handshake input and output data interface.
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Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- The ODT-ADS-7B64G-3 is an ultra-high-bandwidth time-interleaved ADC designed in a 3nm CMOS process.
- This 7-bit, 64GSPS ADC supports ac-coupled input signals up to Nyquist and features a full-scale range of 0.45Vpp differential, excellent dynamic performance, and low noise operation.
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Fault Tolerant DDR2/DDR3/DDR4 Memory controller
- FTADDR is a memory controller for DDR2,DDR3 and DDR4 SDRAM memory devices.
- It uses a strong error correction code to achieve exceptional fault tolerance
UCIe Controller IP View All
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UCIe Die-to-Die Chiplet Controller
- High configurability and customizability
- Defines packets to communicate with a link partner using different AXI parameters
- Supports raw streaming modes
- Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
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UCIe PHY & D2D Adapter
- 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
- UCIe v1.1 specification
PCIe 7.0 IP View All
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PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/completion traffic
- Handles up to 4 TLPs per cycle
- Advanced PIPE modes and port bifurcation
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PCIe 7.0 PHY IP
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
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PCIe 7.0 PHY in TSMC (N5, N3P)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SSC)
AI IP View All
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RISC-V CPU IP
- RISC-V RVA23 Compliant
- >18 SPECint2006/GHz
- 8-wide decode unit
- Advanced branch predictor
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NPU IP for Embedded ML
- Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
- Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
- Future proof architecture that supports the most advanced ML data types and operators
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Future-proof IP for training and inference with leading performance per watt and per dollar
- RISC-V-based AI IP development for enhanced training and inference.
- Silicon-proven solutions tailored for AI workload optimization.
- Energy-efficient performance with industry-leading Perf/W.
MIPI IP View All
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
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MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
RISC-V IP View All
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32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
- 32/64 Bit RISC-V core
- 5-stage pipeline
- In-order, Single issue
- Multicore Capable (up to 8 cores)
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Dual-issue Linux-capable RISC-V core
- 64-bit RISC-V core
- RVA22 profile
- Linux capable
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High-performance RISC-V CPU
- Fully compliant with the RVA23 RISC-V specification
- Comparable PPA to Arm Neoverse V3 / Cortex-X4
- Standard AMBA CHI.E coherent interface for SoC and chiplet integration
- Co-architected with Veyron E2 for seamless vector, AI acceleration, and big-little style heterogeneous compute configurations