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ADC / DAC IP

Most of the signals directly encountered in science and engineering are continuous: light intensity that changes with distance; voltage that varies over time; a chemical reaction rate that depends on temperature, etc. ADC IPs (Analog-to-Digital Converter) and DAC IPs (Digital-to-Analog Converter) are the IP cores that allow digital designs to interact with these everyday signals.

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Search (747)
Compare 747 ADC / DAC IP from 63 vendors (1 - 10)
  • 14b 560kS/s pipeline ADC
    • Effective Number of Bits: 13.5b (SNDR=83dB signal-to-noise-and-distortion-ratio)
    • Power supply 3.3V, Power Consumption 2,4mW
    • 0.35um CMOS Technology
    • Low input sampling capacitor of 4pF
    Block Diagram -- 14b 560kS/s pipeline ADC
  • 12b 1MS/s serial ADC
    • Effective Number of Bits: 11b (SNDR=68dB signal-to-noise-and-distortion-ratio)
    • Power supply 3.3V
    • 0.35um CMOS Technology
    • Low input sampling capacitor of 7pF
    Block Diagram -- 12b 1MS/s serial ADC
  • 15b 4kS/s serial ADC
    • Effective Number of Bits: 15b (SNDR=92dB signal-to-noise-and-distortion-ratio) with digital IIR filter post-processing
    • Power supply 3.3V, Power Consumption 200µW
    • 0.35um CMOS Technology
    • Low input sampling capacitor of 4pF
    Block Diagram -- 15b 4kS/s serial ADC
  • 14b 30kS/s serial ADC
    • Effective Number of Bits: 13.5b (SNDR=83dB signal-to-noise-and-distortion-ratio)
    • Power supply 3.3V, Power Consumption 170µW
    • 0.35um CMOS Technology
    • Low input sampling capacitor of 4pF
    Block Diagram -- 14b 30kS/s serial ADC
  • 20b-linear 100MS/s DAC on X-FAB 180nm SOI
    • Implementation technology: X-FAB 180nm SOI (XT018) 5+1 Metal, Double-MiM Cap for high linearity and low temp. coeff.
    • Architecture: digital oversampling Sigma-Delta Modulator with 38 current-steering cells and 2stage analog RC reconstruction filtering with two fully differential Voltage Amplifiers
    • Power Supply: 1.8Vdd analog & digital core, 5Vdd analog power output
    • 20bit 10MS/s digital input interpolated (10x, 20x) to 100MS/s as oversampling Sigma-Delta Modulator input
    Block Diagram -- 20b-linear 100MS/s DAC on X-FAB 180nm SOI
  • 6-bit, 5 GSPS DAC - GlobalFoundries, 22FDX
    • The D6B5G is ultra-low power, high-speed digital to analog converter (DAC) intellectual property (IP) block.
    • It has a 6-bit resolution, and a sampling speed of 5 gigasamples per second (GSPS).
    Block Diagram -- 6-bit, 5 GSPS DAC - GlobalFoundries, 22FDX
  • 12-bit, 10 GSPS DAC - GlobalFoundries GF22FDX
    • The D12B10G is an ultra-low power, high-speed digital to analog converter (DAC) intellectual property (IP) block.
    • It is a 12-bit current steering DAC with maximum sampling rate of 10 gigasamples-per-second (GSPS).
    Block Diagram -- 12-bit, 10 GSPS DAC - GlobalFoundries GF22FDX
  • 12-bit ADC on Samsung 8nm LN08LPP
    • The sf_adc0802x_ln08lpp_306011 is a 1.8V/0.75V dual supply-voltage 16-ch 12-bit analog-to-digital converter (ADC) that supports conversion rate (FS) up to 1MS/s, designed in 8nm CMOS FinFET process.
    • It consists of a 16-to-1 analog input MUX, a successive approximation (SAR) type monolithic ADC, a clock generator, and level-shifters for low voltage digital interface.
    Block Diagram -- 12-bit ADC on Samsung 8nm LN08LPP
  • 12-bit ADC on Samsung 4nm LN04LPE
    • ADC0401X is a 1.2-V/0.75-V dual supply voltage 16-channel 12-bit Analog-to-Digital Converter (ADC) that supports conversion rate (FS) up to 1 MS/s, designed in 4-nm CMOS FinFET process.
    Block Diagram -- 12-bit ADC on Samsung 4nm LN04LPE
  • 11-bit, 5 GSPS SAR ADC - GlobalFoundries GF22FDX
    • The A11B5G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block.
    • It is a hybrid-SAR ADC, with 11-bit resolution and a sampling rate of 5 gigasamples-per-second (GSPS).
    Block Diagram -- 11-bit, 5 GSPS SAR ADC - GlobalFoundries GF22FDX
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