Serdes IP

2x to 4x throughput at 50% or less energy consumption as compared to conventional SerDes over the same number of pins/wires
High pin-efficiency and low power
208.3 Gbit/s full-duplex bandwidth per mm of die edge (500 Gbit/s for 2.4 mm of die edge)

The 64G SerDes PHY is a highly configurable PHY capable of supporting speeds up to 64Gbps within a single lane
The PHY has been configured to support 64G PAM-4 and NRZ specifically, but the PHY itself can be configured to support a wide range of HS SerDes protocols through changes to the PCS layer and register settings

The 32G SerDes PHY is a highly configurable IP solution capable of supporting data rates of up to 32 Gbps per lane
It is designed to accommodate a wide range of high-speed SerDes protocols, including PCIe, USB, Rapid IO, XAUI, SATA, Ethernet, and JESD204B/C, through flexible PCS layer configurations and programmable register settings
The PHY is architected to support multi-lane implementations, featuring a shared common block that integrates a Tx PLL, reference clock input, bandgap, bias circuitry, and termination calibration

4 Channels per Quad, ≤64Gbps; PAM4 support 25~64Gbps; NRZ support 2.5~32Gbps
Serialization/Deserialization interface width; 64/32/16bits; 64-bit parallel data path in PAM4 mode; 32-bit parallel data path in full-rate NRZ mode; 16-bit and 32-bit parallel data path widths in half-rate and quarter-rate modes
Four programmable transmitter and receiver configurations selectable by port by using hardware pins or registers. Facilitates fast speed switching during speed negotiation routines
Aggressive equalization capability to enable 64Gbps operation and legacy system upgrades

8 Channels per Macro, 2.5Gbps~112Gbps with TX/RX independent; NRZ Data Rate:2.5-56Gbps PAM4 Data Rates: 56-112Gbps
Serialization/Deserialization interface width; PCS-User interface support 64bit in PIPE
Two cascaded PLLs, one LC-tank based and the other ring-oscillator based
Digitally-control-impedance termination resistors

Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
Compact form factor – 0.116 mm2 active silicon area per lane including ESD
Industry leading low power – typically 6.3 mW/Gbps (@6Gbps) including termination
Minimal latency – 3 UI between parallel transfer and serial transmission

Optimized Performance, Power and Area with Design Agility
Supports full-duplex 1.25 to 225Gbps data rates
Enables 1.6T, 800G, 400G, and 200G Ethernet with a PHY + Controller solution
Supports evolving IEEE 802.3 and OIF-CEI-224G standard electrical specifications
Meets the performance requirements of chip-to-module (VSR), chip-to-chip (MR), and copper/backplane (LR) interconnects