Serdes IP

Designed with a small footprint, ultra-low latency, and low power consumption, the 112G SerDes maximizes bidirectional memory access efficiency, reduces software complexity, and helps chip developers leverage existing Ethernet infrastructure to significantly lower Total Cost of Ownership (TCO).
Featuring IEEE 802.3-compliant Forward Error Correction (FEC), 35dB ultra-high channel loss compensation, and adaptive high-speed equalization technologies (CTLE, FFE), it provides full-cycle link protection—from error correction to pre-warning—enabling highly compatible, stable, and efficient chip-to-chip connectivity solutions.

YouPHY-Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstrate good performance class performance, area and power.
The programmable PHY supports major standards such as PCIe Gen 4.0/3.0/2.0/1.0, USB 3.1/3.0, XAUI, SATA Gen 3.0/2.0/1.0, CEI-11G-LR, 10GBase-KX4, JESD204B, SGMII/QSGMII, RAPID I/O, HSSTP (Trace Port), V-By-One, DisplayPort and HMC.

The 100G SERDES PHY IP for VSR supports up to 100 Gbps data rate with low-power consumption and a small footprint.
It has advanced features such as equalization, and clock and data recovery, ensuring reliable data transmission.
The IP can be integrated into a variety of applications such as networking, data centers, and high-performance computing.

The LVDS_SERDES IP Core is a high-speed LVDS transmitter / receiver pair suitable for a wide range of serial interface applications.
The design is comprised of an independent transmitter and receiver that may be used separately or together as a single transceiver.

4 Channels per Quad, ≤64Gbps; PAM4 support 25~64Gbps; NRZ support 2.5~32Gbps
Serialization/Deserialization interface width; 64/32/16bits; 64-bit parallel data path in PAM4 mode; 32-bit parallel data path in full-rate NRZ mode; 16-bit and 32-bit parallel data path widths in half-rate and quarter-rate modes
Four programmable transmitter and receiver configurations selectable by port by using hardware pins or registers. Facilitates fast speed switching during speed negotiation routines
Aggressive equalization capability to enable 64Gbps operation and legacy system upgrades

8 Channels per Macro, 2.5Gbps~112Gbps with TX/RX independent; NRZ Data Rate:2.5-56Gbps PAM4 Data Rates: 56-112Gbps
Serialization/Deserialization interface width; PCS-User interface support 64bit in PIPE
Two cascaded PLLs, one LC-tank based and the other ring-oscillator based
Digitally-control-impedance termination resistors

The MXL4254A is a silicon proven Quad Gigabit SerDes implemented in digital CMOS technology. Each of the four channels supports data rate up to 4.25 Gbps.It is compatible with router-backplane links, PCI Express, SATA, RapidIO, 10 Gbps Ethernet (XAUI), FibreChannel, SFI-5, SPI-5, and other communication applications.

2x to 4x throughput at 50% or less energy consumption as compared to conventional SerDes over the same number of pins/wires
High pin-efficiency and low power
208.3 Gbit/s full-duplex bandwidth per mm of die edge (500 Gbit/s for 2.4 mm of die edge)