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Serdes IP

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Search (156)
Compare 156 Serdes IP from 33 vendors (1 - 10)
  • 32Gbps SerDes PHY in GF 22nm
    • This 32Gbps SerDes PHY is implemented in GlobalFoundries 22FDX CMOS technology and provides a high-performance, protocol-agnostic serial interface for advanced mixed-signal and high-speed digital SoCs.
    • The PHY is architected as a modular design consisting of a low-jitter clock multiplier, a half-rate transmitter with digitally programmable feed-forward equalization, and a configurable CTLE-based receiver with digital clock-and-data recovery, supporting both 16 Gbps and 32 Gbps operation.
    Block Diagram -- 32Gbps SerDes PHY in GF 22nm
  • Ultra-Low Latency 32Gbps SerDes IP in TSMC 12nm FFC
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Ultra-low latency 2/4/8-bit parallel interface mode for lowest possible latency
    Block Diagram -- Ultra-Low Latency 32Gbps SerDes IP in TSMC 12nm FFC
  • Ultra-Low Latency 32Gbps SerDes IP in TSMC 22nm ULP
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Ultra-low latency 2/4/8-bit parallel interface mode for lowest possible latency
    Block Diagram -- Ultra-Low Latency 32Gbps SerDes IP in TSMC 22nm ULP
  • 32Gbps SerDes IP in TSMC 12nm FFC
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Configurable low latency parallel data interface for optimal system performance
    Block Diagram -- 32Gbps SerDes IP in TSMC 12nm FFC
  • 32Gbps SerDes IP in TSMC 22nm ULP
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Configurable low latency parallel data interface for optimal system performance
    Block Diagram -- 32Gbps SerDes IP in TSMC 22nm ULP
  • 20G MSS (Multi-standard SerDes) PHY
    • Developing under SF4X CMOS technology (2025.06.30 MTO)
    • Compliant to multiple standards, max datarate 20Gb/s
    • Channel Configuration for Data Lanes: 1, 2 or 4 Data Lanes
    • Reliable Ring OSC PLL based architecture for Low power consumption
    Block Diagram -- 20G MSS (Multi-standard SerDes) PHY
  • 100G SerDes PAM4 PHY
    • The SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps.
    • It supports diverse applications including AI accelerators, data centers, 5G infrastructure, and automotive SoCs.
    Block Diagram -- 100G SerDes PAM4 PHY
  • Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
    • TSMC IP9000 Alliance member enabling automotive IP support in TSMC automotive processes
    • Automotive Documentation including Safety Manual, FMEDA and DFMEA
    • Design reliability report containing EM/IR and Aging analysis
    Block Diagram -- Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
  • 112G Multi-SerDes
    • Designed with a small footprint, ultra-low latency, and low power consumption, the 112G SerDes maximizes bidirectional memory access efficiency, reduces software complexity, and helps chip developers leverage existing Ethernet infrastructure to significantly lower Total Cost of Ownership (TCO).
    • Featuring IEEE 802.3-compliant Forward Error Correction (FEC), 35dB ultra-high channel loss compensation, and adaptive high-speed equalization technologies (CTLE, FFE), it provides full-cycle link protection—from error correction to pre-warning—enabling highly compatible, stable, and efficient chip-to-chip connectivity solutions.
    Block Diagram -- 112G Multi-SerDes
  • Multi-Rate Serdes IP Solution
    • YouPHY-Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstrate good performance class performance, area and power.
    • The programmable PHY supports major standards such as PCIe Gen 4.0/3.0/2.0/1.0, USB 3.1/3.0, XAUI, SATA Gen 3.0/2.0/1.0, CEI-11G-LR, 10GBase-KX4, JESD204B, SGMII/QSGMII, RAPID I/O, HSSTP (Trace Port), V-By-One, DisplayPort and HMC.
    Block Diagram -- Multi-Rate Serdes IP Solution
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