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Serdes IP

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Search (153)
Compare 153 Serdes IP from 30 vendors (1 - 10)
  • 64G High-speed SerDes
    • The 64G SerDes PHY is a highly configurable PHY capable of supporting speeds up to 64Gbps within a single lane
    • The PHY has been configured to support 64G PAM-4 and NRZ specifically, but the PHY itself can be configured to support a wide range of HS SerDes protocols through changes to the PCS layer and register settings
    Block Diagram -- 64G High-speed SerDes
  • 32G SerDes
    • The 32G SerDes PHY is a highly configurable IP solution capable of supporting data rates of up to 32 Gbps per lane
    • It is designed to accommodate a wide range of high-speed SerDes protocols, including PCIe, USB, Rapid IO, XAUI, SATA, Ethernet, and JESD204B/C, through flexible PCS layer configurations and programmable register settings
    • The PHY is architected to support multi-lane implementations, featuring a shared common block that integrates a Tx PLL, reference clock input, bandgap, bias circuitry, and termination calibration
    Block Diagram -- 32G SerDes
  • Ultra-short reach SerDes with 500 Gbit/s throughput
    • 2x to 4x throughput at 50% or less energy consumption as compared to conventional SerDes over the same number of pins/wires
    • High pin-efficiency and low power
    • 208.3 Gbit/s full-duplex bandwidth per mm of die edge (500 Gbit/s for 2.4 mm of die edge)
    Block Diagram -- Ultra-short reach SerDes with 500 Gbit/s throughput
  • 25/28/32G Combo SerDes
    • 4 Channels per Quad
    • Data rate up to 25/28/32Gbps
    • Shared Quad LC-PLL for high performance
    • Independent Ring-PLL of each channel for clock flexibility
    Block Diagram -- 25/28/32G Combo SerDes
  • 64G SerDes
    • 4 Channels per Quad, ≤64Gbps; PAM4 support 25~64Gbps; NRZ support 2.5~32Gbps
    • Serialization/Deserialization interface width; 64/32/16bits; 64-bit parallel data path in PAM4 mode; 32-bit parallel data path in full-rate NRZ mode; 16-bit and 32-bit parallel data path widths in half-rate and quarter-rate modes
    • Four programmable transmitter and receiver configurations selectable by port by using hardware pins or registers. Facilitates fast speed switching during speed negotiation routines
    • Aggressive equalization capability to enable 64Gbps operation and legacy system upgrades
    Block Diagram -- 64G SerDes
  • 112G SerDes USR & XSR
    • 8 Channels per Macro, 2.5Gbps~112Gbps with TX/RX independent; NRZ Data Rate:2.5-56Gbps PAM4 Data Rates: 56-112Gbps
    • Serialization/Deserialization interface width; PCS-User interface support 64bit in PIPE
    • Two cascaded PLLs, one LC-tank based and the other ring-oscillator based
    • Digitally-control-impedance termination resistors
    Block Diagram -- 112G SerDes USR & XSR
  • Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
    • Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
    • Compact form factor – 0.116 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.3 mW/Gbps (@6Gbps) including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    Block Diagram -- Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
  • SerDes IP
    • 10dB to 35dB bump-to-bump insertion loss
    • Multi-rate support for 56Gbps to 112Gbps PAM4 and NRZ
    • Integrated PLL
    • Robust clock distribution architecture
    • Advanced mixed signal analog equalization architecture
    • Fully adaptive and programmable RX equalization
    • Auto-negotiation
    • Link Training
    Block Diagram -- SerDes IP
  • Ethernet SerDes - 16Gbps and 10Gbps multi-protocol SerDes PHY
    • Wide range of protocols that support networking, HPC, and applications
    • Low-latency, long-reach, and low-power modes
    • Multi-Link PHY—mix protocols within the same macro
    • EyeSurf —non-destructive on-chip oscilloscope
    • Extensive set of isolation, test modes, and loop-backs including APB and JTAG
    • Supports 16-bit, 20-bit, and 32-bit PIPE and non-PIPE interfaces
    • Selectable serial pin polarity reversal for both transmit and receive paths
    Block Diagram -- Ethernet SerDes - 16Gbps and 10Gbps multi-protocol SerDes PHY
  • 224G-LR SerDes PHY enables 1.6T and 800G networks
    • Optimized Performance, Power and Area with Design Agility
    • Supports full-duplex 1.25 to 225Gbps data rates
    • Enables 1.6T, 800G, 400G, and 200G Ethernet with a PHY + Controller solution
    • Supports evolving IEEE 802.3 and OIF-CEI-224G standard electrical specifications
    • Meets the performance requirements of chip-to-module (VSR), chip-to-chip (MR), and copper/backplane (LR) interconnects
    Block Diagram -- 224G-LR SerDes PHY enables 1.6T and 800G networks
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