A Golden Source As The Single Source Of Truth In HSI
The hardware/software interface (HSI) is where system-on-chip (SoC) software defines the connections between the software and the underlying hardware. Maintaining a precise, synchronized HSI across all artifacts is challenging, and unmanaged deviations can propagate through the flow and affect integration schedules.
Most complex SoCs rely on IP reuse, each with its own naming conventions, hand-edited spreadsheets, wikis, and scripts that can fragment and drift quickly. This could create a disconnect between the software’s view of the device and what the silicon implements. Teams must also manage bug fixes and evolving standards. To mitigate risk, Arteris technology automates generation from a golden source input, keeping the HSI consistent across RTL, drivers, verification, documentation, and firmware.
From source to system
Arteris products provide a solution by capturing the HSI in a machine-readable format and updating all dependent artifacts on every build. Using Magillem Connectivity and Magillem Registers, teams package IP, compose system maps, elaborate registers, and produce synchronized outputs, including netlists, UVM RAL, C headers, and HTML documentation, all from the same description. Generators and checkers operate together to catch connectivity errors and conflicts early in the process.
By generating all outputs from a single source and automatically validating them, Arteris builds consistency into the process. IP is packaged with interface metadata, parameters, clocks/resets, and legal settings. Hierarchical address maps contain other address maps. Leaf maps contain registers and memories. Because Magillem supports IP-XACT and SystemRDL/CSRSpec, the same description can instantiate components, elaborate the address space, and emit synchronized views for all stakeholders.
To read the full article on Semiconductor Engineering, click here.
Related Semiconductor IP
- Smart Network-on-Chip (NoC) IP
- FlexNoC 5 Interconnect IP
- FlexNoC Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults.
- NoC Verification IP
- NoC System IP
Related Blogs
- Want to Mix and Match Dies in a Single Package? UCIe Can Get You There
- Imagination and Renesas Redefine the Role of the GPU in Next-Generation Vehicles
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- The Role of GPU in AI: Tech Impact & Imagination Technologies
Latest Blogs
- CAVP-Validated Post-Quantum Cryptography
- The role of AI processor architecture in power consumption efficiency
- Evaluating the Side Channel Security of Post-Quantum Hardware IP
- A Golden Source As The Single Source Of Truth In HSI
- ONFI 5.2: What’s new in Open NAND Flash Interface's latest 5.2 standard