Interface Security IP
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Interface Security IP
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72
Interface Security IP
from 17 vendors
(1
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10)
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TLS Handshake Hardware Accelerator
- RSA, ECC and more
- > 1 GHz in 16nm
- 400-500 MHz on mid-range/high-end FPGA
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DDR Encrypter
- Protect the external memory
- On-the-fly encryption
- Optional authentication
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Memory & Bus Protection IP Core
- The Memory & Bus Protection IP Core module enables on-the-fly encryption/decryption and authentication to the external memory.
- It supports AHB/AXI slave/master interfaces, APB port for configuration purpose, and contains a cache. It is typically placed between the processor(s) and an external memory controller (DDRx).
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Crypto Coprocessor (Compact)
- The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
- Symmetric operations are offloaded very efficiently as it has a built-in scatter/gather DMA. The coprocessor can be used to accelerate/offload IPsec, VPN, TLS/SSL, disk encryption, or any custom application requiring cryptography algorithms.
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Crypto Coprocessor (Premium)
- The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
- Symmetric operations are offloaded very efficiently as it has a built-in scatter/gather DMA. The coprocessor can be used to accelerate/offload IPsec, VPN, TLS/SSL, disk encryption, or any custom application requiring cryptography algorithms.
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Crypto Coprocessor (Standard)
- The Crypto Coprocessors are a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA or ASIC.
- Symmetric operations are offloaded very efficiently as it has a built-in scatter/gather DMA. The coprocessor can be used to accelerate/offload IPsec, VPN, TLS/SSL, disk encryption, or any custom application requiring cryptography algorithms.
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Inline Decrypter IP Core
- XIP (eXecution In Place) of encrypted code directly from Flash. (Optional xSPI controller)
- Decryption based on AES fully compliant with NIST FIPS 197
- AMBA Master/Slave interfaces
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Network Security Crypto Accelerator
- Scalable architecture & crypto engines for optimal performance/resource usage
- Configurable for perfect application fit
- 100% CPU offload with low latency and high throughput
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1-port Receiver/Transmitter HDCP 2.3 on DisplayPort 1.4/2.0 ESM (generation 3)
- Transmitter (TX) or Receiver (RX) solution
- Silicon-proven. Widely deployed. Certified.
- HDCP 2.3 compliant for premium content protection
- DisplayPort 2.0/1.4 support
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Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
- One input word per clock without any backpressure
- Design can switch stream, algorithm, mode, key and/or direction every clock cycle
- GCM: throughput is solely determined by the data width, data alignment and clock frequency
- XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available
