LCD Controller IP

Advanced display processing, such as Multi-layer Overlay Windows with composition features such as Alpha Blending, Color Space Conversion, 4:2:0 and 4:2:2 YCrCb color with Re sampling & conversion to RGB, Frame Buffer Compression and Hardware Cursor

The Display Controller Verilog RTL IP Core comes in releases supporting baseline display processing features and releases with advanced display processing, such as Multi layer Overlay Windows with optional Alpha Blending, Scaling, Color Space Conversion, 4:2:0 and 4:2:2 YCrCb with Re-sampling & conversion to RGB, and Hardware Cursor and Frame Buffer Compression. Optional features provide the customer with targeted features while saving on VLSI resources and licensing costs.
The DB9000AXI3 contains a selectable 256 / 128 / 64 / 32-bit AXI Master Interface with the higher data widths targeting higher resolution, higher color depth LCD or OLED display panels, with their resulting high frame buffer memory data bandwidth requirements.

The Digital Blocks DB9000AHB-Lite TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 3.0 AHB-Lite Bus V1.0 to a TFT LCD panel.
In an FPGA, ASIC, or ASSP device, the microprocessor is typically an ARC, ARM, Intel, MIPS, OpenSPARC, PowerPC, or Tensilica processor and frame buffer memory is either on-chip SRAM memory or larger off-chip SRAM or SDRAM.

The DB9000AHB TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 AHB Bus to a TFT LCD panel.
In an FPGA, ASIC, or ASSP device, the microprocessor is an ARM processor and frame buffer memory is either on-chip SRAM memory or larger off-chip SRAM or SDRAM.

The DB9000AXI-DCI LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconnect to a 4K and 2K Digital Cinema Initiative (DCI) High Definition TFT LCD panel
The video image in frame buffer memory can be 8/10/12-bit YCrCb or RGB, with a Color Space Convert to match the source video to the TFT LCD panel requirements

The DB9100AHB BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to combining existing bitmaps on and off-screen using one of 256 Raster Operations.
A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT).
The DB9100AHB also contains a Monochrome Bitmap Color Expansion feature, typically used for font expansion of compressed character bitmaps.
A 1-bit depth bitmap is expanded to one of two colors, a foreground or background color, with the foreground color representing the text, and the background color the non-text background.

The DB9100AXI BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to combining existing bitmaps on and off-screen using one of 256 Raster Operations.
A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT).
The DB9100AXI also contains a Monochrome Bitmap Color Expansion feature, typically used for font expansion of compressed character bitmaps. A 1-bit depth bitmap is expanded to one of two colors, a foreground or background color, with the foreground color representing the text, and the background color the non-text background.

The DB9100AVLN BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to combining existing bitmaps on and off-screen using one of 256 Raster Operations.
A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT).

The DB6845 CRT Controller core is a full function equivalent to the Motorola MC6845 device.
The DB6845 interfaces a microprocessor to a raster-scan CRT display. The microprocessor access 19 registers (1 Address and 18 Data Registers) within the DB6845 in order to provide video timing, refresh memory addresses, cursor, and light pen strobe signals.
CRT video timing signals include Vertical Sync (VS), Horizontal Sync (HS), and Display Enable (DE) output signals. Refresh memory addressing includes Memory Address (MA[13:0]) and Row Address (RA[4:0]) output buses.