Peripheral IP

The Universal Timers System is a programmable and highly configurable device that comprises seven submodules: Pulse Width Modulation (PWM), Timer 1, Timer 2, Timer 3, Real-Time Interrupt (RTI), Computer Operates Properly (COP), Pulse Accumulator (PA)

The AMBA 3 AHB-Lite Verification IP provides an effective & efficient way to verify the components interfacing with AMBA®3 AHB-Lite bus of an IP or SoC.
The AMBA 3 AHB-Lite VIP is fully compliant with standard AMBA 3 AHB-Lite specification from ARM.
This VIP is a light weight VIP with easy plug-andplay interface so that there is no hit on the design cycle time.

The AMBA AXI3 Verification IP provides an effective & efficient way to verify the components interfacing with AMBA® AXI3 bus of an IP or SoC.
The AMBA AXI3 VIP is fully compliant with standard AMBA® AXI3 specification from ARM.
This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design cycle time.

This IP integrates both xSPI (Expanded Serial Peripheral Interface) and eMMC 5.1 PHY (Physical Layer) into a single unified solution, enabling support for two distinct memory protocols within the same IP.
By combining the PHY layers for both interfaces, the design simplifies system integration, reduces area and pin count, and enhances design flexibility for SoCs that require both boot and high-speed storage functionality.

The BRIDGE_UART_I2C IP Core provides a simple and convenient way to interface a standard UART bus to a standard I2C bus.
The circuit operates as a completely transparent ‘bridge’ between the two buses and allows I2C peripherals to be programmed using a set of basic commands over a (UART) serial interface.

The SONY_CAM_IF IP Core provides a simple way to connect the Sony® FCB-EV range of cameras to your FPGA.
It serves as a direct replacement for an external LVDS receiver IC and takes advantage of the fast LVDS I/O solutions provided by modern FPGA devices.

The SPI_SLAVE IP Core is an SPI compliant slave interface controller. The controller decodes the bus signals and de-serializes them into a series of 8-bit bytes.
Communication with the slave controller is achieved by programming a single control register and a single address register.

The CODEC_8B10B IP Core is a scalable 8B/10B Encoder/Decoder pair suitable for a wide range of serial data transmission applications.
The design is optimized for very high-speed operation and is suitable for use in serial data links of 6 GHz+ on basic FPGA devices.

The AC97-CTRL Audio Controller is a configurable IP block designed to simplify the integration of the AC'97 audio interface into ASIC and FPGA designs.
Fully compliant with the Intel Audio Codec '97 (AC’97) Revision 2.3 specification, this controller facilitates reliable transmission and reception of stereo or multi-channel audio streams using the well-established AC-Link interface.
With support for a single codec operating at a standard 48 kHz sample rate, the core is ideal for embedded applications that demand proven audio infrastructure with a compact silicon footprint and efficient data handling.

CVI is a fully Customizable Video Input controller IP core.
The video input controller can be applied to e.g. FPGA systems with a resource optimized, application specific feature configuration or to ASIC projects applying a more generic feature set and thus more flexibility.