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Search (989)
Compare 989 Peripheral IP from 90 vendors (1 - 10)
  • xSPI - PSRAM Master
    • SPI Protocol:
    • AXI4 Slave
    • AXI4 DMA Master
    • AXI4 – LITE SLAVE
    Block Diagram -- xSPI - PSRAM Master
  • I3C Host Controller
    • Compliant with MIPI I3C Specification V1.0
    • Supports up to 12.5 MHz operation using Push-Pull.
    Block Diagram -- I3C Host Controller
  • Tessent Bus Monitor
    • Full transaction and trace-level visibility of on-chip bus traffic
    • Wide range of measurements, analytics statistics: Transactions, Bus cycles, latency, duration, beats, bus concurrency
    • Supports AXI, ACE, ACE-lite
    • Run-time configurable
    Block Diagram -- Tessent Bus Monitor
  • PCIe 5.0 Controller with AXI
    • Comprises complete PCIe 5.0 interface subsystem with Rambus PCIe 5.0 PHY
    • Supports the PCI Express 5.0 rev. 1.0 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s) and PIPE (8, 16, 32 and 64-bit) specifications
    • Supports the PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
    • Supports Endpoint, Root-Port, Dual-mode configurations
    Block Diagram -- PCIe 5.0 Controller with AXI
  • PCIe 4.0 Controller with AXI
    • Internal data path size automatically scales up or down (64-, 256- bits) based on link max. speed and width for reduced gate count and optimal throughput
    • Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs up to Gen4 x8/Gen3 x16 with same RTL code
    • Stringent implementation of PCIe to AXI Ordering Rules and AXI to PCIe Ordering Rules guarantees AXI deadlock prevention
    • Carefully engineered AXI bridge & AXI interconnect allows full performance on AXI interfaces
    Block Diagram -- PCIe 4.0 Controller with AXI
  • AHB Octal SPI Controller with Execute in Place
    • Compatible with many industry-standard serial FLASH devices
    • Execute-in-place (XIP)
    • AMBA AXI4 interface
    Block Diagram -- AHB Octal SPI Controller with Execute in Place
  • Quad SPI Controller
    • Configurable SPI modes
    • Supports programmable SPI clocking modes
    • Programmable interrupt on SPI-done
    Block Diagram -- Quad SPI Controller
  • CodaCache® Last Level Cache IP
    • Standalone IP
    • 1.2 GHz frequency in 16FF+TT process
    • Protocol interoperability: AMBA AXI 4
    Block Diagram -- CodaCache® Last Level Cache IP
  • xSPI Master IP | NOR IP
    • JESD 251 compliant
    • JEDEC SFDP Compliant
    Block Diagram -- xSPI Master IP | NOR IP
  • Path tracing/Ray tracing accelerator
    • Powerful Path Tracing Acceleration GPU IP Solution
    • ‘Unified’ Traversal and Intersection Test
    • Based on High Performance MIMD Architecture
    • Highly Applicable for Servers and High End GPU Chips
    Block Diagram -- Path tracing/Ray tracing accelerator
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