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RapidIO IP

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Compare 15 RapidIO IP from 9 vendors (1 - 10)
  • Rapid IO - Physical Layer Interface Core
    • The RapidIO™ is a packet - switched interconnect intended primarily as an intra - system interfaces for a chip-to-chip and board-to-board communications at Gigabyte per second performance levels.
    • Developed as an open standard, the RapidIO™ architecture addresses the needs of present and future systems.
    • RapidIO™ is focused as a processor, memory and memory mapped I / O interfaces optimized for use inside the chassis.
    Block Diagram -- Rapid IO - Physical Layer Interface Core
  • RapidIO Intel® FPGA IP
    • Intel is discontinuing the intellectual property (IP) for RapidIO I and RapidIO II, more information can be found in the product discontinuance notification (PDN2025).
    Block Diagram -- RapidIO Intel® FPGA IP
  • RapidIO Verification IP (VIP)
    • The RapidIO Verification IP (VIP) provides highly capable compliance verification solution for the RapidIO protocol.
    • The RapidIO VIP is system Verilog (SV) based and supports standard Universal Verification Methodology (UVM).
    • It can be easily combined with any other UVM compliant verification components to extend a broader verification environment.
    Block Diagram -- RapidIO Verification IP (VIP)
  • RapidIO to AXI Bridge (RAB)
    • The RapidlO-AXI Bridge (RIO-AXI Bridge) is a highly flexible and configurable IP used along with the native RapidlO Controller (GRIO) to provide RapidlO interface on one side and AXI interface on the system side.
    • The Bridge has been architectured to interface with a RapidlO controller used as a Host or device.
    • The RIO-AXI BRIDGE uses high speed multi-channel DMA Messaging and data streaming controllers to match the bandwidth requirements of the RIO solution.
    Block Diagram -- RapidIO to AXI Bridge (RAB)
  • RapidIO Controller with V4.1 Support
    • The RapidlO Controller solution (GRIO™) is a highly flexible and configurable IP.
    • The RapidlO Controller Solution can be used as a Host or device.
    • The RapidlO Controller when used along with the RapidlO to AXI Bridge (RAB) provides high speed multi-channel DMA Data Message and Data streaming functionality to match the bandwidth requirements of the RapidlO interface.
    Block Diagram -- RapidIO Controller with V4.1 Support
  • Rapid IO 4.0/3.1/2.2 PHY
    • 4 Channel per Quad
    • Shared Quad common PLL architecture
    • Digitally-control-impedance termination resistors
    • Configurable TX output differential voltage swing
    Block Diagram -- Rapid IO 4.0/3.1/2.2 PHY
  • RapidIO Verification IP
    • Supports RapidIO specification 1.3, 2.0, 2.1, 2.2, 3.0, 3.1, 3.2, 4.0 and 4.1.
    • Supports Serial 1x/2x/4x/8x and 16x Physical lanes.
    • Supports 8b/10b and 64b/67b Encode and Decode functions.
    • Supports scrambler/Descrambler.
    Block Diagram -- RapidIO Verification IP
  • RapidIO Synthesizable Transactor
    • Supports RapidIO specification 1.3, 2.0, 2.1, 2.2, 3.0, 3.1, 3.2, 4.0 and 4.1.
    • Supports Serial 1x/2x/4x/8x and 16x Physical lanes.
    • Supports 25.78125Gbaud/s, 12.5Gbaud/s, 10.3125Gbaud/s, 6.25Gbaud/s, 5Gbaud/s,3.125 Gbaud/s, 2.5 Gbaud/s, 1.25 Gbaud/s.
    • 8b/10b Encode and Decode functions.
    Block Diagram -- RapidIO Synthesizable Transactor
  • RAPIDIO EndPoint Controller IIP
    • Compliant with RapidIO Interconnect 2.2 specification
    • Supports all Capability Registers(CARs) and Configuration and Status Registers(CSRs)
    • Supports high link utilization and low latency
    • Supports efficient receive and transmit buffering scheme
    Block Diagram -- RAPIDIO EndPoint Controller IIP
  • Serial RapidIO 2.1 Endpoint IP Core
    • LatticeECP3 AMC Evaluation board
    • Associated cables
    • AMC interface card
    • Demonstration bitstreams and files
    Block Diagram -- Serial RapidIO 2.1 Endpoint IP Core
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