Image Codec
Welcome to the ultimate Image Compression IP Cores hub! Explore our vast directory of Image Compression IP.
Image Compression IP Cores consist of JPEG, JPEG 2000, JPEG-LS and CCSDS IP cores that offer maximum image quality and performance.
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Image Codec
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Lossless & Lossy Frame Compression IP
- The CFrame60 is a Lossless & Lossy Frame Compression Hardware IP, Designed to significantly reduce memory size, DRAM bandwidth and power.
- This ultra-small, highly flexible IP consists of a set of compression IP and decompression IP, with the ability to easily switch between lossless and lossy.
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Video Interlacer
- The INTERLACER IP Core is a fully pipelined video interlacer solution that converts any progressive video format into its interlaced equivalent.
- The format of the input video is defined by the parameters pixels_per_line and lines_per_frame.
- These values specify the size of one input frame of video in pixels and lines. Each interlaced output field will have half the number of lines as an input frame.
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High-Definition SMPTE Test Pattern Generator
- The HD_SMPTE_TPG IP Core is a versatile test pattern generator capable of producing a range of test patterns in 20-bit 4:2:2 format.
- The output stream format is compliant with the SMPTE standards 296M and 274M.
- The module is ideal for use in the prototyping stages of digital video systems or as a known good reference source for standard 720p, 1080p or 1080i video.
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SMPTE Decoder with Colour-Space Converter
- The HD_SMPTE_DECODER IP Core is a digital video decoder with integrated colour-space converter.
- It's function is to extract the valid pixels from a standard SMPTE video stream and convert them to 24-bit RGB pixels for subsequent processing.
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High-Definition SMPTE Encoder with Colour-Space Converter
- The HD_SMPTE_ENCODER IP Core is a digital video encoder with integrated colour-space converter.
- The encoder accepts 24-bit RGB pixels from sequential frames.
- These pixels are then mapped to the YCbCr colour-space and formatted correctly into a SMPTE video output stream.
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Graphics Processor Overlay IP Core
- Technology independent soft IP Core for FPGA, ASIC and SoC devices
- Supplied as human-readable VHDL (or Verilog) source code
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OpenGL ES 2.0 3D graphics IP core for FPGAs and ASICs
- D/AVE NX is the latest and most powerful addition to the D/AVE family of rendering cores.
- It is the first IP to bring 3D graphics OpenGL ES 2.0 rendering (with some ES 3.0 / 3.1 extensions) to the FPGA and SoC world and – with offline-shader compilers – even into MCUs or low-end MPUs with small amounts of memory and bare-metal or RTOS operation systems.
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3D OpenGL ES 1.1 GPU IP core
- D/AVE 3D is cost-efficient IP core for 3D graphics applications.
- This core is available for FPGAs, ASICs and SOCs, specifically designed for the embedded, automotive and infotainment market with a big emphasis on flexibility both in hardware and the software.
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2.5D GPU
- The D/AVE HD 2.5D GPU family is an evolution of the D/AVE 2D family supporting high quality 2D and 3D rendering for displays up to 4K x 4K.
- Targeting modern graphics applications on high resolution displays in the Industrial, Medical, Military, Avionics, Automotive and Consumer markets, the D/AVE HD fixed-function 2.5D GPU core is designed to be fast with powerful functionality.
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JPEG encoder
- Baseline JPEG compliant (ITU T.81), Motion JPEG
- Up to 12 bits depth possible (default: 8 bit)
- Super low latency (less than 1/10 of frame duration for rolling shutter cameras)
- Lossy compression by default
- Fully bit and cycle accurate co-simulation model available in Docker container
