Clock Generator IP

Compare 13 Clock Generator IP from 8 vendors (1 - 10)

General Purpose Fractional-N PLL in GlobalFoundries 22FDX
- Super small: 80 x 80 microns!
- Very low power: 12-mW
- Broad frequency range: 6-GHz
Minimum-area low-power clocking PLL (1st gen)
- - Super small: 80 x 80 microns!
- - Very low power: 12-mW
- - Broad frequency range: 2-GHz
- - Fast lock
High Speed Integer PLL IP
- Up to 4Ghz clock output
- Wide range of multiplicand
- Small physical area
- TEST pin integrated
APB Real Time Clock
- Clock / Calendar (BCD Format)
- Alarm Mode for each “Time Unit”.
- Repeat Alarm Mode for each “Time Unit”.
- AMBA APB Interface.
syn1588® enabled IEEE 1588 compliant clock synchronisation
- fully synchronous to the system clock
- all registers of the core operate with the rising clock edge
- well commented, structured VHDL source code
- medium footprint and medium I/O count
General Purpose Fractional-N PLL in TMSC 16FFC
- Low jitter (< 18ps RMS)
- Small size (< 0.005 sq mm)
- Low Power (< 1.7mW)
Clock-Reset Generator
- up to 16 programmable dividers
- dividers can change ratio "on-the fly"
- each divider provides up to 16 gated clocks and 1 ungated
- PLL software control - restart for changing frequency, stop mode, bypass mode
Run Time Phase Alignment Circuit
- 1. Sync Clock Generation in one clock duation.
- 2. Generatted clock is Phase Aligned with the incoming data. Data can be received.
- 3. Tx and Rx Clock can be up to +/-5% off of the frequency range. This block can accomode and can generate same tx freq at the rx side.
- 4. This Rx Clock can be used to -
High-Speed Digital PLL (0.5-7.5 GHz) in TSMC 40G CMOS
- Wide range and programmability (0.5GHz to 7.5GHz)
- Predictability
- Easy Porting
- Size (0.11mm^2)
Low noise from 8GHz to 11.3GHz differential LC VCO
- Phase noise -108dB typical
- Single 1.2V Power Supply
- VCO center frequencies 8.5GHz, 10.0GHz, 10.7GHz, 11.1GHz
- Each VCO frequency tuning ±8%