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Compare 17 IP for Intel Foundry from 3 vendors (1 - 10)
  • General-purpose & Specialized Ring PLLs + RTL-based Solutions
    • Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
    • Input & output frequency ranges greater than 1000:1
    Block Diagram -- General-purpose & Specialized Ring PLLs + RTL-based Solutions
  • PVT SENSOR
    • SGC21713_IP007708_GF_22FDX can be used in a control loop to minimize the voltage for a given frequency or maximize frequency for a given voltage
    • Based on a group of sensors, it permits PVT and aging tracking, while allowing the identification of the actual variable that changed
    • Designed to achieve 3% overall accuracy (over Load / Line / Temp), it is specified from TJ = –40°C to +125°C.
    Block Diagram -- PVT SENSOR
  • Sleep Management Subsystem
    • Power-On-Reset
    • Programmable relaxation oscillator
    • Low Power Comparator
    Block Diagram -- Sleep Management Subsystem
  • Power Management Subsystem
    • The agilePMU Subsystem is an efficient and highly integrated Power Management Unit for SoCs/ASICs.
    • Featuring a Power-On-Reset (POR), multiple Low Drop-Out (LDO) regulators, and an associated reference generator.
    • The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities.
    Block Diagram -- Power Management Subsystem
  • Sensor Interface Subsystem
    • The agileSensorIF Subsystem is an efficient and highly integrated sensor interface for SoCs/ASICs.
    • Featuring multiple Analog-to-Digital Converters (agileADC), Digital-to-Analog Converters (agileDAC), low-power programmable analog comparators (agileCMP_LP), and an associated reference generator (agileREF).
    • The agileSensorIF Subsystem enables easy interaction with the analog world.  
    Block Diagram -- Sensor Interface Subsystem
  • Temperature Sensor (Analog Output)
    • The agileTSENSE_A GP Temperature Sensor is a traditional ΔVBE temperature sensor that amplifies the difference between two VBE voltages, and converts the result to a single-ended signal.
    • This temperature sensor can be used with the agileADC in order to provide a digital output with an overall relative accuracy of +/-0.25°C.
    • On modern SoCs, thermal management is critical for detection of security attacks and optimization of power, performance and area.
    Block Diagram -- Temperature Sensor (Analog Output)
  • General Purpose BandGap Reference
    • The agileREF consists of a bandgap reference core together with a bandgap reference voltage generator (VREF), VREF replica current generators and bias current generators.
    • The number of output bias currents can be specified up to a maximum of 16 configurable outputs.
    • There is an integrated test bus.
    Block Diagram -- General Purpose BandGap Reference
  • RC Oscillator
    • The agileRCOSC is based on a traditional architecture which allows for the frequency to be trimmed to remove the effects of process variation.
    •  This can also be configured as a Free Running Clock (FRC) where a high accuracy clock is not required.
    Block Diagram -- RC Oscillator
  • Power-On-Reset Circuit
    • The agilePOR GP is a Power-On-Reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis to avoid false resets in noisy environments.
    Block Diagram -- Power-On-Reset Circuit
  • Low Power Regulator
    • The agileLDO_LP is a linear regulator, suitable for use in any low power, low current system and is designed to provide a flexible range of regulated output voltages suitable for ultra-low power systems and near-vt operating modes.
    • The agileLDO_LP consists of: A voltage reference generator, an error amplifier and a output current source. The regulated output voltage is fed-back into the error amplifier to maintain a constant regulated output over the specified range of input voltages and load currents.
    Block Diagram -- Low Power Regulator
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