UCIe Die-to-Die Chiplet Controller

Overview

The UCIe Controller IP is a highly configurable and customizable UCIe 1.1 compliant die-to-die controller. It extends on-chip AXI interconnections to multi-die connections, providing an advanced solution for multi-die connectivity across various applications. The controller uses flits, which are flow control units that are both reliable and latency-optimized. In addition, OUC ensures that the receiver buffer does not overflow at the receiver end. With its well-defined AXI packet structure, the OUC seamlessly matches AXI parameters with its link partner, ensuring smooth format matching and communication even with different AXI parameters. OUC matches the protocol using padding and cropping with default operation rules defined in AXI.

This UCIe chiplet brings highly customizable, package-level integration with die-to-die interconnect and protocol connections, creating an interoperable, multi-vendor ecosystem, and establishing a new industry standard for universal interconnect at the package level.

Key Features

  • AXI over UCIe Streaming Protocol
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
  • Link Error Detection and Retry Feature
    • Implements CRC and retry mechanisms
    • Handles parity error effectively
  • APB for Controller Control
    • Manages parameter setup
    • Controls link operations
    • Facilitates test and debug processes

Benefits

  • Configurability
    • AXI interface including widths and signals
    • RDI/FDI data width (32byte/16byte)
    • Flit format
    • Address map
  • Simulation Model
    • Supports host bus integration
    • Includes software layer for UCIe controller
    • Facilitates Design Space Exploration (DSE) for UCIe switching fabric
    • Enables traffic generation for performance estimation
  • High Operation Frequency
    • Achieves 1+GHz operating frequency on SEC 5nm automotive process
    • Configured with 32B FDI/RDI data width
  • Verification Environment
    • Features UCIe controller loop-back environment with traffic generator and checker for on-chip validation
    • Integrates UCIe Controller and PHY

Block Diagram

UCIe Die-to-Die Chiplet Controller Block Diagram

Applications

  • Automotive
  • Ai accelerators
  • AI/ML
  • high computing and servers, etc

Deliverables

  • OUC is packaged with the following items to all eligible companies:
    • IP core RTL
    • Standalone Simulation Environment
    • Management SW
    • IP Documentation

Technical Specifications

Availability
Available on request
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Semiconductor IP