IP Catalog > DSP & Math IP > Error Correction/Detection IP

Error Correction/Detection IP

Error Correction/Detection IP cores are specialized hardware modules designed to enhance the reliability and integrity of data transmission and storage in embedded systems. These cores implement advanced error detection and correction algorithms, such as Hamming codes, Reed-Solomon, and BCH, to identify and correct errors in data, ensuring accurate and secure communication. Ideal for applications in memory systems, communication networks, and high-performance computing, Error Correction/Detection IP cores help prevent data corruption, reduce system downtime, and improve overall system performance.

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Search (248)
Compare 248 Error Correction/Detection IP from 41 vendors (1 - 10)
  • SDA OCT V3.0 Encoder and Decoder
    • Compliant with "Optical Communications Terminal (OCT) Standard Version 3.0, Document ID: SDA-9100-0001-05, August 2021"
    • Support for payload code rates 11/13, 22/29, 2/3, 1/2, and uncoded data
    Block Diagram -- SDA OCT V3.0 Encoder and Decoder
  • IEEE 802.3bj Reed-Solomon Encoder and Decoder
    • Compliant with IEEE 802.3bj, Clause 91
    • Support for KR4 (528, 514) and KP4 (544, 514) Reed-Solomon (RS) code
    • Corrects up to seven (KR4) or up to 15 (KP4) erroneous symbols
    Block Diagram -- IEEE 802.3bj Reed-Solomon Encoder and Decoder
  • NCR Processor
    • NCR (Network Clock Reference) is a procedure to provide the master clock (i.e. time information) of the satellite to all its user terminals.
    • Typically, NCR packets are provided periodically over a continuous DVB-S2 or DVB-S2X link.
    • The receiving user terminal uses the knowledge of the master clock in the system to determine when it is allowed to transmit data in a time-division multiple access (TDMA) system, such as DVB-RCS or DVB-RCS2.
    Block Diagram -- NCR Processor
  • DVB-GSE Encapsulator and Decapsulator
    • The DVB-GSE encapsulator and decapsulator IP cores close the gap between network protocols like Ethernet and the physical layer of the DVB family of standards.
    • The DVB-GSE encapsulator performs the encapsulation of the network layer packets, also referred to as Protocol Data Units (PDUs), into one or more GSE packets, adding control information and performing integrity checks when necessary. 
    Block Diagram -- DVB-GSE Encapsulator and Decapsulator
  • LDPC Decoder for 5G NR and Wireless
    • The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance.
    • It employs the Min-Sum LDPC decoding algorithm to ensure efficient decoding.
    • The core allows for programmable internal bit widths at compile time, though the default values are usually sufficient.
    Block Diagram -- LDPC Decoder for 5G NR and Wireless
  • LDPC Encoder/Decoder (LDPC)
    • Supporting a wide range of data-rates
    • 50MB/s to 4.0GB/s for a single LDPC instance
    • Scalable platform provides the basis for customer specific custom-LDPC cores
    Block Diagram -- LDPC Encoder/Decoder (LDPC)
  • eMMC LDPC Encoder/Decoder
    • Supports data rates from 50 MB/s to 9.0 GB/s.
    • Enables custom LDPC core development for specific requirements.
    • Wide range of codeword sizes.
    • Maximum supported parity.
    Block Diagram -- eMMC LDPC Encoder/Decoder
  • VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
    • VESA DisplayPort 1.4 compliant
    • Reed-Solomon RS (254,250) FEC, 10-bit symbols
    • Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
    • DisplayPort main 8b/10b encoder included (Tx only)
    • Status and control can be done with signals or optionally via an integrated APB register module (Rx)
    Block Diagram -- VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
  • Reed Solomon FEC
    • Designed to support any Reed Solomon code.
    • Custom tailored to support specific codes see standard table below
    • Low Latency
    • FEC Processing cycles optimized for reduced buffering
    Block Diagram -- Reed Solomon FEC
  • LDPC Encoder/Decoder IP Core
    • IPM-LDPC for NandFlash Storage: Adaptable BER, Up to 6 checks per bit, customizable data path
    • IPM-LDPC for short code: option to be full asynchronous, option to be in 3 clock cycles
    • fully configurable: matrix generator, data path, number of iteration checks, packet size
    Block Diagram -- LDPC Encoder/Decoder IP Core
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