LunaNet AFS LDPC Encoder and Decoder IP Core
The IP Core implements LunaNet LDPC code for Lunar Augmented Navigation Services.
- Channel Coding
Channel Coding IP cores accelerate forward error correction and coding functions in communication systems in modern SoC and ASIC designs.
These IP cores implement coding and decoding primitives used to improve reliability over noisy channels in wireless, wired, and storage applications
This catalog allows you to compare Channel Coding IP cores from leading vendors based on coding throughput, latency, supported code families, and process node compatibility.
Whether you are designing wireless baseband, satellite links, storage systems, or network infrastructure, you can find the right Channel Coding IP for your application.
LunaNet AFS LDPC Encoder and Decoder IP Core
The IP Core implements LunaNet LDPC code for Lunar Augmented Navigation Services.
3GPP compliant coding and modulation for Downlink Physical Shared Channels The Physical Downlink Shared Channel (PDSCH) is used f…
DVB-RCS2 Multi-Carrier Receiver
DVB-RCS2 (Digital Video Broadcast – Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second…
3GPP compliant coding and modulation for Physical Shared Channels The Physical Uplink Shared Channel (PUSCH) is used to for uplin…
The DVB-S2-LDPC-BCH block is a FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite.
CCSDS SCCC Turbo Encoder and Decoder
The recommended CCSDS 131.2-B-1 standard introduces a Serial Concatenated Convolutional Code (SCCC).
DVB-S2X Wideband BCH and LDPC Decoder
The DVB-S2X wideband decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 500 Msymb/s on FPGAs.
DisplayPort 1.4 FEC Receiver (Rx)
The DisplayPort Forward Error Correction (FEC) Receiver IP core implements Reed-Solomon FEC and symbol interleaving as specified …
DOCSIS 3.1 LDPC Decoder (PLC / NCP / Data)
Data Over Cable Service Interface Specification (DOCSIS) is an international telecommunications standard that permits the additio…
IEEE 802.3bj Reed-Solomon Encoder and Decoder
IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic.
Mobiveil’s 50G PON LDPC Encoder/Decoder offers industry- LDPC error correction in a low-power, small-footprint, high-reliability …
The DVB-S2X decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 100 MSymbols/s on FPGAs.
WCDMA Release 9 compliant Viterbi Decoder
The Lekha IP – 3GPP WCDMA Viterbi Decoder IP Core V1.0 addresses the implementation of the Viterbi Decoder defined as part of the…
High bit rate Turbo Decoder core for 3GPP LTE/ LTE A
The Lekha IP – 3GPP LTE Turbo Decoder IP Core V1.0 addresses the decoder implementation for the turbo coded transport channel com…
Generic Open Source Viterbi Decoder
Convolutional codes are widely adopted in wireless communication systems for forward error correction.
The BCH decoder has four main functional blocks along with memory blocks.
The K-best decoder is part of the MIMO decoder.
Nand Flash write cycles are limited.
LDPC (1723,2048) core is compliant with IEEE Standard 802.3.2018 Ethernet specification.
FEC RS (544,514) core is compliant with standard CPRI 7.0 Specification, IEEE Standard 802.3.2018 Ethernet specification and JESD…