IP Catalog > DSP & Math IP > Error Correction/Detection IP

Error Correction/Detection IP

Error Correction/Detection IP cores are specialized hardware modules designed to enhance the reliability and integrity of data transmission and storage in embedded systems. These cores implement advanced error detection and correction algorithms, such as Hamming codes, Reed-Solomon, and BCH, to identify and correct errors in data, ensuring accurate and secure communication. Ideal for applications in memory systems, communication networks, and high-performance computing, Error Correction/Detection IP cores help prevent data corruption, reduce system downtime, and improve overall system performance.

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Search (243)
Compare 243 Error Correction/Detection IP from 39 vendors (1 - 10)
  • DVB-S2-LDPC-BCH
    • Irregular parity check matrix
    • Layered decoding
    • Minimum sum algorithm
    • Soft decision decoding
    • BCH decoder works on GF (2m) where m=16 or 14 and corrects up to t errors, where t = 8, 10 or 12
    Block Diagram -- DVB-S2-LDPC-BCH
  • BCH Decoder
    • BCH decoder compliant with the DVB-T2/S2 standard.
    • Available for Altera/Xilinx FPGA or ASIC implementation.
    • High speed design.
    • BCH decoder works on GF(2M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
    • Area and power optimized implementation.
    Block Diagram -- BCH Decoder
  • LDPC Decoder IS-GPS-800D
    • Irregular parity check matrix
    • Layered Decoding
    • Minimum sum algorithm
    • Configurable number of iterations
    • Soft decision decoding
    Block Diagram -- LDPC Decoder IS-GPS-800D
  • Reed Solomon
    • High performance Reed Solomon IP Core (Encoder and Decoder).
    • Supports error and erasure decoding.
    • Parameterized codeword length.
    • Code generator polynomial: (x + λ^0 )(x + λ^1 )(x + λ^2 )...(x + λ^15 ).
    Block Diagram -- Reed Solomon
  • Viterbi Decoder
    • Supports 1/N coderates
    • Configurable constraint length
    • Configurable generator polynomials
    • Configurable precision of state metrics
    Block Diagram -- Viterbi Decoder
  • oFEC Encoder and Decoder
    • OpenROADM oFEC (Open Forward Error Correction) is a core element of the OpenROADM initiative, providing a standardized, open-source FEC solution for high-speed coherent optical networks.
    • The oFEC IP cores deliver high coding gain through a fully parallel, pipelined decoder architecture with 3 soft-decision (SD) and 2 hard-decision (HD) decoding steps. It supports data rates from 200G to 800G, including Probabilistic Constellation Shaping (PCS) modes to enhance spectral efficiency, noise tolerance, and transmission reach.
    Block Diagram -- oFEC Encoder and Decoder
  • Polar Encoder / Decoder for 3GPP 5G NR
    • The patented polar encoding and decoding IP for the 3GPP New Radio uplink and downlink includes the entire processing chain, to provide quick and easy integration and minimize the amount of extra work needed.
    • The polar core uses PC- and CRC-aided SCL polar decoding techniques, in order to achieve compromise-free error correction performance.
    Block Diagram -- Polar Encoder / Decoder for 3GPP 5G NR
  • LDPC Encoder / Decoder for 3GPP 5G NR
    • The LDPC decoder product suite has been specifically designed as flexible IP to address the unique challenges of 5G NR across all use cases covered by the current standards, deliver market leading performance and efficiency, and be easily integrated into designs.
    Block Diagram -- LDPC Encoder / Decoder for 3GPP 5G NR
  • DVB-Satellite modulator
    • The CMS0035 DVB-Satellite Modulator is an integrated core featuring our DVB-S/-DSNG modulator (CMS0010) and DVB-S2/-S2X modulator (CMS0025) cores. The CMS0035 core provides all the functionality required to address the requirements of the ETSI forward-link satellite Standards EN 300 421 (DVB-S), EN 301 210 (DSNG), EN 302 307-1 (DVB-S2) and EN 302 307-2 (DVB S2X), with additional support for DVB-S2X VLSNR operation
    • The core can operate in a constant coding-and-modulation (CCM) mode for all Standards and in the enhanced variable-coding-and modulation (VCM) and adaptive-coding-and modulation (ACM) modes provided by DVB-S2 and DVB-S2X.
    Block Diagram -- DVB-Satellite modulator
  • DVB-S2 modulator
    • The CMS0025 DVB-S2/S2X Modulator with integrated LDPC encoder has been designed specifically to address the requirements of the ETSI DVB-S2 forward-link satellite standard (EN 302 307), section-1 together with the section-2 extensions (DVB-S2X), with additional support for DVB-S2X VLSNR operation. The core can operate in CCM and VCM/ACM modes.
    • The core provides all the necessary processing steps to modulate a single transport stream (or baseband frame) into a complex I/Q signal for input to a pair of DACs, or an interpolating DAC device such as the AD9857(or AD9957). Optionally, the output can be selected as an IF to supply a signal DAC.
    Block Diagram -- DVB-S2 modulator
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