InCore Calcite is a 32/64 Bit RISC-V in-order, single-issue 5-stage pipelined micro-processor. Built on Incore's proprietary deep-customization stack for microarchitectural exploration, Calcite delivers an optimal balance between power and performance in an exceptionally small silicon footprint.
The Calcite core comes bundled as a compute subsystem, with integrated AMBA protocol interconnects (supports AXI4, AHB) and uncore components (PMU, debug, interrupt controllers etc).
32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.
Overview
Key Features
- An in-order 5-stage 64/32-bit processor
- Supports RISC-V ISA: RV[64|32]IMAFDCSU [HBP]
- Single issue
- Targets mid-range compute systems: 500-800MHz
- Supports RISC-V Linux, secure L4
- Variants for low-power and high-performance
- Positioned against ARM Cortex A5/A35
- MMU and PMP support
- Single and Double Precision Floating point units compliant with IEEE-754
- Supports the OpenOCD based debug environment through JTAG
- Non-invasive Debug architecture
Benefits
- Configurability
- Over 2000 optimal design points
- Custom RISC-V extensions supported
- Time to Market
- Compute subsystem (core, interconnect, uncore) to quick-start SoC development
- PPA
- Industry-beating performance and area
Block Diagram
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Applications
- IoT
- IP Camera
- AR/VR
- POS terminals
- Wearables
Deliverables
- RTL (Verilog)
- Fully synthesizable
- Human-readable
- Documentation:
- Datasheet
- User Guide
- Integration Guide
- Architecture Reference Guide
- Programmer's Guide
- Hardware Development Kit (HDK):
- FPGA: Xilinx bitstream
- Verification test suites
- ASIC: Synthesis and Constraints scripts
- Software Toolchain:
- GCC Cross Compiler
- GDB
- Open OCD
- Assembler
- Disassembler
- Linker
- Instruction Set Simulator
Technical Specifications
Foundry, Node
Any
Maturity
Silicon Proven
Availability
Available
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