32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA.

Overview

InCore Calcite is a 32/64 Bit RISC-V in-order, single-issue 5-stage pipelined micro-processor. Built on Incore's proprietary deep-customization stack for microarchitectural exploration, Calcite delivers an optimal balance between power and performance in an exceptionally small silicon footprint.

The Calcite core comes bundled as a compute subsystem, with integrated AMBA protocol interconnects (supports AXI4, AHB) and uncore components (PMU, debug, interrupt controllers etc).

Key Features

  • 32/64 Bit RISC-V core
  • 5-stage pipeline
  • In-order, Single issue
  • Multicore Capable (up to 8 cores)
  • Available in many versions:
    • RV32I[M][C][F][B][U]
  • Profiles supported:
    • RVI20U32
    • RVI20U64
    • RVA20U64
    • RVA20S64
  • 32 general purpose registers
  • Multiplier
    • Iterative (fixed latency or early-out)
    • Fast multiply (2-cycle)
  • RISC-V privilege mode support:
    • Machine
    • User
    • Supervisor
  • Optional FPU (single precision, double precision)
  • Optional 8 or 16 PMP regions
  • Memory Management Unit
    • Supports Sv32, Sv38, Sv48 and Svnapot extensions
  • Optional L1 data and instruction caches
  • Optional L2 cache
  • Optional Internal interrupt controller
    • Up to 128 sources
  • Optional Standard RISC-V CLINT
  • Optional NMI
  • RISC-V Debug module
  • 2/4 pin JTAG
  • 2-8 breakpoints/watchpoints

Benefits

  • Configurability
    • Over 2000 optimal design points
    • Custom RISC-V extensions supported
  • Time to Market
    • Compute subsystem (core, interconnect, uncore) to quick-start SoC development
  • PPA
    • Industry-beating performance and area

Block Diagram

32b/64b RISC-V 5-stage, scalar, in-order, Application Processor. Linux and multi-core capable. Maps upto ARM A-35. Optimal PPA. Block Diagram

Applications

  • Linux Devices
  • Consumer Electronics
  • IoT
  • Wearables
  • Terminals
  • Multimedia
  • IP Camera
  • Storage Controllers
  • Mixed Signal Embedded

Deliverables

  • RTL (Verilog)
    • Fully synthesizable
    • Human-readable
  • Documentation:
    • Datasheet
    • User Guide
    • Integration Guide
    • Architecture Reference Guide
    • Programmer's Guide
  • Hardware Development Kit (HDK):
    • FPGA: Xilinx bitstream
    • Verification test suites
    • ASIC: Synthesis and Constraints scripts
  • Software Toolchain:
    • GCC Cross Compiler
    • GDB
    • Open OCD
    • Assembler
    • Disassembler
    • Linker
    • Instruction Set Simulator

Technical Specifications

Foundry, Node
Any
Maturity
Silicon Proven
Availability
Available
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Semiconductor IP