Interface IP Cores

Avery TSN Ethernet Verification IP provides a complete simulation-based func tional verification solution for core-level and SoC-level verification, including MAC and PHY models, protocol checking, and optional compliance test suite based on UNH-IOL test specifications.
Additional integration with ARM® Fast Model integration enables running the TSN IP’s software stack in one fully integrated testbench.

Accelerated confidence in simulation-based verification of RTL designs with PCI Express (PCIe) interfaces: PCIe Gen2/3/4/5/6/7

Accelerated confidence in simulation-based verification of RTL designs with Compute Express Link (CXL) interfaces: CXL1, CXL2, CXL3, CXL3.1

The SPI/xSPI/QSPI/OSPI Verification IP provides an effective & efficient way to verify the components interfacing with SPI/QSPI/OSPI interface of an ASIC/FPGA or SoC.
VIP environment encapsulates the SPI/xSPI/QSPI/OSPI compatible UVM based Master, compatible Slave, BUS monitor & Scoreboard.

The AXI Bridge with DMA IP core is the ultimate PCIe DMA IP solution with a powerful mix of multiple industry standard AXI Interfaces.
AXI Stream interfaces allow continuous data streaming from FPGA to Host or from Host to FPGA. S-AXI Memory mapped interfaces allow easy data access of remote memories in order to realize shared memory access or per to peer applications.

The Multi-Channel AXI DMA engine IP Core for AXI4 is a powerful programmable AXI Stream to AXI memory mapped bridge with sophisticated data addressing options.
These features allow data accesses on a tile basis in order to address regions of interest (ROI) based applications like stereo cameras, 2D picture compression algorithms and others.

The AXI Bridge for PCIe IP core is the IP solution with a powerful mix of multiple industry standard memory mapped AXI Interfaces.
The AXI Bridge IP core translates the AXI4 memory read or writes to PCI-Express Transaction Layer Packets and translates PCIe memory read and write requests to AXI4 transactions.
All interfaces support fully parallel operation without any interferences. Interfaces that are not required can be turned off individually and do not occupy logic resources.

4 Channels per Quad, ≤64Gbps; PAM4 support 25~64Gbps; NRZ support 2.5~32Gbps
Serialization/Deserialization interface width; 64/32/16bits; 64-bit parallel data path in PAM4 mode; 32-bit parallel data path in full-rate NRZ mode; 16-bit and 32-bit parallel data path widths in half-rate and quarter-rate modes
Four programmable transmitter and receiver configurations selectable by port by using hardware pins or registers. Facilitates fast speed switching during speed negotiation routines
Aggressive equalization capability to enable 64Gbps operation and legacy system upgrades

8 Channels per Macro, 2.5Gbps~112Gbps with TX/RX independent; NRZ Data Rate:2.5-56Gbps PAM4 Data Rates: 56-112Gbps
Serialization/Deserialization interface width; PCS-User interface support 64bit in PIPE
Two cascaded PLLs, one LC-tank based and the other ring-oscillator based
Digitally-control-impedance termination resistors