Interface IP Cores

Leveraging the benefits of USB 10Gbps and 5Gbps device controller, USB 20Gbps is designed using the FPGA built-in transceiver.
It is a one-stop solution for all USB requirements ranging from USB 3.2 to USB 2.0.
It supports SuperSpeed+ (SSP x2/x1), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes.
The Core architecture allows to use minimal pins from FPGA for USB 3.2 interface with better stability.

The USB 2.0 On-The-Go (OTG) IP Core is a 32-bit Avalon interface compliant core and supports ULPI interface.
It supports both USB Host and USB Device peripheral functionality.
While acting as USB Host, it supports High Speed (HS), Full Speed (FS) and Low Speed (LS) modes.
While acting as USB Device peripheral, it supports High Speed (HS) and Full Speed (FS) modes.

Leveraging the benefits of USB 3.2 Gen 1 device controller, USB 3.2 Gen 2 is designed using the FPGA built-in transceiver.
It is a one-stop solution for all USB requirements ranging from USB 3.2 to USB 2.0.
It supports SuperSpeed+ (SSP), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes.

I²S Controller is designed to transfer audio data to and from Audio codec.
It can be configured as both Master and Slave mode using software.
The I²S IP is Phillips Inter IC Sound (I²S) specification compliant core for Altera devices.

The I²C slave IP is fully synthesizable core and compatible with Phillips I²C standard. The IP uses I²C Bus Protocol which helps maximize the hardware efficiency and minimize the interfaces.
The I²C Slave IP Core is provided as Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system.

Avalon compliant I²C Master IP core provides an interface between Nios II processor and an I²C Slave device.
It can work as a master transmitter or master receiver depending on working mode determined by Nios II processor.
The I²C Master IP core incorporates all features required by the latest I²C specification including clock synchronization, arbitration, multi-master systems and fast-speed transmission mode.

I²C (Inter-Integrated Circuit) Controller is a two-wire, bi-directional serial bus that provides simple and efficient method of data transmission over a short distance between many devices.
Avalon compliant I²C Controller provides an interface between Nios II processor and I²C device.
It can work as Master/Slave transmitter or Master/Slave receiver depending on working mode determined by Nios II processor.

The USB 2.0 Hub IP core provides a link between the USB2.0 Host and multiple USB peripherals via UTMI + Low pin interface (ULPI).
It supports High speed, Full speed and Low speed peripheral devices.
Its rich features and ease of use makes it more suitable for embedded applications.

USB 2.0 device, FIFO interface (USB20HF) IP Core provides FIFO interface for endpoints and ULPI interface for Host communication.
It supports 15 IN and OUT endpoints as per the USB standards which are configurable in Bulk, Interrupt and Isochronous modes as per the requirement.
The core supports High Speed (480 Mbps), Full Speed (12 Mbps) and Low Speed (1.5 Mbps) functionality. It comes with three pre-configured endpoints - Control, Bulk IN, and Bulk OUT.

The USB 2.0 Device, Software Enumeration (USB20SR) IP Core is a RAM based USB 2.0 device core with 32-bit Avalon/AXI/AHB Lite interface and ULPI interface support.
The core supports High Speed(480 Mbps) , Full Speed(12 Mbps) and Low Speed(1.5 Mbps) functionality.