Interface IP Cores

Support testbench language interfaces for SystemVerilog, UVM, OVM, e, and SystemC
Callbacks access at multiple TX and RX queue points for scoreboarding, data manipulation, and error injection
Transaction Tracker: Configurable tracking of all the transactions on the channels

The Ultra Accelerator Link (UALink) Verification IP (VIP) provides a complete bus functional model (BFM) with integrated automatic protocol checks for physical layer in addition to Media Independent Interface (MII).
Designed for easy integration in testbenches at IP, SoC, and system levels, the VIP helps engineers reduce time to first test, accelerate verification closure, and ensure end-product quality.

The MIPI SoundWire I3S Manager IP enables efficient, low-power, and high-fidelity audio data transfer for mobile, consumer, and automotive applications.
Compliant with the MIPI SoundWire I3S (Inter-IC Sound) standards, it supports synchronized, multi-channel audio over a scalable two-wire interface, ideal for connecting digital microphones, amplifiers, and codecs in space-constrained designs.

The MIPI SoundWire I3S Peripheral IP delivers seamless, low-power, and high-quality audio connectivity for a range of mobile, consumer, and automotive devices.
Fully compliant with the MIPI SoundWire I3S (Inter-IC Sound) specifications, it enables synchronized, multi-channel audio communication with a compact and efficient two-wire interface, ideal for integrating digital microphones, amplifiers, or audio codecs.

Full MIPI SoundWire I3S Master, Slave and Monitor functionality
Supports MIPI Soundwire-I3S Bus Draft Specification v0.4r06.
Supports system with one master and one or more slaves (upto 8 slaves).
Supports LVDS PHY for higher speed and a single-ended CMOS PHY for lower speed systems.

The eDP 2.0 Verification IP provides an effective & efficient way to verify the components interfacing with the eDP interface of an ASIC/FPGA or SoC.
The eDP VIP is fully compliant with the Standard eDP Version 2.0 specifications from VESA.
This VIP is a lightweight VIP with an easy plug-and-play interface, so that there is no hit on the design time and the simulation time.

Designed with a small footprint, ultra-low latency, and low power consumption, the 112G SerDes maximizes bidirectional memory access efficiency, reduces software complexity, and helps chip developers leverage existing Ethernet infrastructure to significantly lower Total Cost of Ownership (TCO).
Featuring IEEE 802.3-compliant Forward Error Correction (FEC), 35dB ultra-high channel loss compensation, and adaptive high-speed equalization technologies (CTLE, FFE), it provides full-cycle link protection—from error correction to pre-warning—enabling highly compatible, stable, and efficient chip-to-chip connectivity solutions.

The ISO/IEC 7816 Verification IP offers a streamlined and efficient solution for verifying System-on-Chip (SoC) and IP designs that incorporate contactless communication.
The ISO/IEC 7816 VIP is compliant with ISO/IEC 7816 Specifications. This VIP is light weight with easy plug-and- play interface so that there is no hit on the design cycle time.

This VIP provides a comprehensive environment for verifying devices acting as either a Proximity Coupling Device (PCD) or a Proximity Integrated Circuit Card (PICC).
Fully compliant with the complete ISO/IEC 14443 standard (Parts 1-4), our VIP is a lightweight, plug-and-play solution designed to ensure rigorous verification, minimize design cycle time, and accelerate your time-to-market.