IP Catalog > Interface IP Cores

Interface IP Cores

Interface IP cores are used to achieve communication between chips and external devices or other chips. Common interface standards include USB, PCIe, SATA, I2C, SPI, Ethernet, etc.

Explore our vast directory of Interface IP cores below.

All offers in Interface IP Cores
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (3,382)
Compare 3,382 Interface IP Cores from 174 vendors (1 - 10)
  • MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
    • Technology is TSMC 22nm ULP 1p10M.
    • Supply voltage can be applied 1.0V for core voltage, 1.8V  for IO voltage.
    • Maximum data rate of each channel is 1.5Gbps at High-speed mode for MIPI D-PHY Transmitter.
    • Data rate of each channel is 609Mbps for FPD-Link(LVDS).
    Block Diagram -- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
  • MIPI D-PHY Transmitter/Receiver for DSI/CSI-2 on Samsung 28nm FD-SOI
    • Technology is Samsung 28nm FD-SOI 8M (6U1x_2T8x_LB).
    • Supply voltage can be applied 1.1V for core voltage, 1.8V for IO voltage.
    • Maximum data rate of each channel is 1.5Gbps at High-speed mode.
    Block Diagram -- MIPI D-PHY Transmitter/Receiver for DSI/CSI-2 on Samsung 28nm FD-SOI
  • MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
    • Renesas MIPI D-PHY Transmitter/Receiver can be used for analog Transmitter/Receiver of following interface.
    • Technology is TSMC 40nm LP 1p6M (4x1z) .
    • Supply voltage can be applied 1.1V for core voltage, 1.8V for IO voltage.
    Block Diagram -- MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
  • Configurable PCI Express 4.0 Link Controller
    • Compliant with "PCI Express™ Base Specification, Rev. 4.0 Version 1.0"
    • Compliant with "PHY Interface For the PCI Express, SATA, and USB3.1 Architectures"
    Block Diagram -- Configurable PCI Express 4.0 Link Controller
  • UDP Offload Engine for IPv4
    • The UDP/IP core implements the UDP/IPv4 standard RFC 768/791, including checksum, segmentation and reassembly hardware offload.
    • The UDP/IP core is tested for operation with popular FPGA vendors’ GbE Ethernet MACs.
    Block Diagram -- UDP Offload Engine for IPv4
  • Ethernet PHY IP
    • Compliant to 802.3 Ethernet specification - 200GBASE-KR4, 200GBASE-CR4, 100GBASE-KR4, 100GBASE-CR4, 100GBASE-KR2, 100GBASE-CR2, 50GBASE-KR, 50GBASE-CR, 40GBASE-KR4, 40GBASE-CR4, 25GBASE-KR, 25GBASE-CR, 10GBASE-KR, 10GBASE-CR
    • Data rate supported - Ethernet: NRZ 3.125 - 26.5625Gb/s, PAM4 53.125Gb/s
    • DSP-based architecture using high-performance ADC/DAC for RX/TX
    Block Diagram -- Ethernet PHY IP
  • 1G BASE-T Ethernet Verification IP
    • The 1G BASE-T Ethernet Verification IP provides deliverables an effective & efficient way to verify the components interfacing with the Ethernet interface of an IP or SoC. 
    •  The 1G Ethernet VIP is fully compliant with the IEEE standard 802.3 specification.
    • This VIP is lightweight with easy plug -and- play interface so that there is no hit on the design cycle time.
    Block Diagram -- 1G BASE-T Ethernet Verification IP
  • DSC Encoder
    • Compliant with VESA DSC 1.2b, backward compatible with DSC 1.1
    • Supports all mandatory and optional coding schemes:
    • Modified Median-Adaptive Prediction (MMAP)
    • Midpoint Prediction (MPP)
    Block Diagram -- DSC Encoder
  • DSC Decoder
    • Compliant with VESA DSC 1.2b, backward compatible with DSC 1.1
    • Supports all mandatory and optional coding schemes:
    • Modified Median-Adaptive Prediction (MMAP)
    • Midpoint Prediction (MPP)
    Block Diagram -- DSC Decoder
  • DP and eDP TX/RX PHY IP
    • eDP v1.5 compliant
    • Supports for 1.62Gbps to Max 8.1Gbps data rate
    • PSR, PSR2 supported for low power consumption ( FW_SLEEP, FW_STANDBY supported )
    • Supports for eDP v1.5 feature such as AUX-less Link Training
    Block Diagram -- DP and eDP TX/RX PHY IP
×
Semiconductor IP