Interface IP Cores

Compare 3,368 Interface IP Cores from 175 vendors (1 - 10)

LPC Verification IP
- The LPC Verification IP provides an effective & efficient way to verify the LPC components of an IP or SoC.
- The LPC VIP is fully compliant with LPC Specification version 1.1
- The VIP is lightweight with easy plug-and-play components so that there is no hit on the design cycle time.
LPC Assertion IP
- Compliant to LPC 1.1 specifications.
- Supports bandwidth upto 33 MHz.
- Supports the following operations
eSPI LPC Bridge IIP
- Compliant with version 1.1 LPC Interface Specifications and eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.0
- Converts eSPI Peripheral Channel Transactions into LPC Memory write or read instructions
- Supports full LPC host capability
- Supports SOC Slave
LPC Device IIP
- Compliant with version 1.1 LPC Specification.
- Full LPC Device/Peripheral functionality
- Supports the following operations:
- Memory read and write
LPC Host IIP
- Compliant with version 1.1 LPC Specifications.
- Full LPC Host functionality.
- Supports the following operations:
- Memory read and write
LPC Synthesizable Transactor
- Compliant to LPC 1.1 specifications.
- Supports bandwidth up to 33 MHz.
- Supports the following operations
- Memory read and write
LPC Verification IP
- Compliant to LPC 1.1 specifications.
- Supports bandwidth up to 33 MHz.
- Supports the following operations.
- Memory read and write
PCIe PHY and controller solution
- Brite 16Gbps PCIe PHY and controller solution provide high efficient interconnection that is optimized for PPA performance. The System can support short-reach or long-reach channels for plenty application scenarios.
- Brite PCIe controller to AXI architecture provides a high-performance, easy-to-use interconnect solution between PCI Express and the latest version of the AXI protocol. It inherits the leading architecture and features an AXI user interface with built-in DMA, compliant with the AMBA® AXI3 and AXI4 specifications.
USB PHY Solution
- Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design.
- The USB2.0 OTG PHY supports the USB2.0 480Mbps protocol and data rate, and is backward compatible with the USB 1.1 1.5Mbps and 12Mbps protocol and data rates.
- It has been verified by a number of end products, especially suitable for the current popular internet of things applications.
MIPI CSI2 Interface Solution
- Brite provides full solution for the MIPI CSI interface, which receives the data from sensors in PHY layer, and then converts the byte data to pixel after lane data mergence.
- Data scramble is an optional feature to decrease the EMI effect.
- A standard PPI interface is implemented for the connection between MIPI PHY and CSI controller. Brite MIPI CSI interface solution supports image applications with varying pixel formats.