IP Catalog > Interface IP Cores

Interface IP Cores

Interface IP cores are used to achieve communication between chips and external devices or other chips. Common interface standards include USB, PCIe, SATA, I2C, SPI, Ethernet, etc.

Explore our vast directory of Interface IP cores below.

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Search (3,401)
Compare 3,401 Interface IP Cores from 173 vendors (1 - 10)
  • MIPI SWI3S Manager Core IP
    • The SWI3S (SoundWire I3S Interface) Manager Controller Core IP implements the link protocol to communicate in half-duplex fashion to transfer the Audio streams and the Control information together.
    • One or more SWI3S Peripheral IP can be connected specific to the application.
    Block Diagram -- MIPI SWI3S Manager Core IP
  • Combo SerDes
    • 4 Channels per Quad
    • Data rate up to 25/28/32Gbps
    • Shared Quad LC-PLL for high performance
    • Independent Ring-PLL of each channel for clock flexibility
    Block Diagram -- Combo SerDes
  • Embedded USB2 (eUSB) Controller + PHY IP
    • Compliant to Embedded USB2 Version2.0, Aug 2024
    • Supports high-speed, full-speed, and low-speed operation.
    • Meet low voltage requirement (1.0V – 1.2V)
    • No change in existing USB2/USB3 Port
    • Supports symmetric and asymmetric data rates
    Block Diagram -- Embedded USB2 (eUSB) Controller + PHY IP
  • CSI-2 v2.1 Receiver IP
    •  Fully compliant to MIPI standard
    • Small footprint
    • Functionality ensured with comprehensive verification
    • Product quality proven with silicon
    Block Diagram -- CSI-2 v2.1 Receiver IP
  • 10G/25G/40G/100Gbit/s Ethernet MAC/PCS
    • 10/25/40/100 Gbit Ethernet Connectivity in Intel and AMD/Xilinx FPGA
    • Designed to IEEE 802.3by specification
    • Low latency, TX 11ns, RX 8ns (Modes: cut-through/store-and-forward)
    • Integrated FCS(CRC32) checker and generator
    Block Diagram -- 10G/25G/40G/100Gbit/s Ethernet MAC/PCS
  • UDP/IP Offload Engine - 10G/25G/40G/100Gbit/s Ethernet UDP/IP
    • AXI4s MAC & Application Interfaces
    • De-fragmentation option available
    • Designed to UDP specification RFC768
    • Compose/Decompose complete UDP Datagrams
    Block Diagram -- UDP/IP Offload Engine - 10G/25G/40G/100Gbit/s Ethernet UDP/IP
  • TCP/IP Offload Engine - 10G/ 25G/40G/100Gbit/s TCP/IP
    • 1 to 256 Simultaneous connections
    • Server/Client roles, configurable per connection
    • Automatically establish & tear-down connections
    • All-RTL send/receive for extremely low latency
    Block Diagram -- TCP/IP Offload Engine - 10G/ 25G/40G/100Gbit/s TCP/IP
  • Ultra Ethernet Verification IP
    • The Ultra Ethernet (UE) Verification IP provides an effective & efficient way to verify the components interfacing with Ethernet interface of an IP or SoC.
    • The UE VIP is compliant with IEEE standard 802.3-2018 & UE Specifications V1.0.
    • This VIP is light weight with easy plug-and-play interface so that there is no hit on the design cycle time.
    Block Diagram -- Ultra Ethernet Verification IP
  • Ethernet Switch VLAN 5x100M
    • 5 x 100 Mbit/s Ethernet ports.
    •  Full wire-speed on all ports and all Ethernet frame sizes.
    •  Store and forward shared memory architecture.
    •  Support for jumbo packets up to 4087 bytes.
    •  Passes maximum overlap mesh test (RFC2899) excluding the CPU port, for all packet sizes up to 1518 bytes.
    Block Diagram -- Ethernet Switch VLAN 5x100M
  • Ethernet Switch Advanced L2/VLAN 48x1G + 5x10G
    • 48 ports of 1 Gigabit Ethernet.
    •  5 ports of 10 Gigabit Ethernet.
    •  Full wire-speed on all ports and all Ethernet frame sizes.
    •  Store and forward shared memory architecture.
    •  Support for jumbo packets up to 16359 bytes.
    Block Diagram -- Ethernet Switch Advanced L2/VLAN 48x1G + 5x10G
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