Interface IP Cores

Interface IP cores are used to achieve communication between chips and external devices or other chips. Common interface standards include USB, PCIe, SATA, I2C, SPI, Ethernet, etc.

Explore our vast directory of Interface IP cores below.

All offers in Interface IP Cores
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Compare 3,412 Interface IP Cores from 178 vendors (1 - 10)
  • USB 2.0 Host IP Core
    • The USB 2.0 Host IP is a USB 2.0 specification compliant host IP core with an optional AHB, PCI, or custom host interface.
    • The USB 2.0 Host IP supports 480 Mbit/s in High Speed (HS) mode. 12 Mbit/s in Full Speed (FS) mode, and 1.5 Mbit/s in Low Speed (LS) mode.
    Block Diagram -- USB 2.0 Host IP Core
  • USB 2.0 Device IP Core
    • High speed support: 480 Mbit/s
    • Full speed support: 12 Mbit/s
    • USB 2.0 Compliant
    • High/Full speed support using 8/16 bit UTMI/ULPI interface
    Block Diagram -- USB 2.0 Device IP Core
  • SLIMbus Host IP V2.0
    • The MIPI SLIMbus Host v2.0 typically resides in a mobile platform’s application processor and provides two-wire, multipurpose connectivity with multiple audio and another low/mid bandwidth peripheral devices.
    • The SLIMbus Host Controller IP is designed to provide MIPI SLIMbus 2.0 compliant connectivity to an SoC.
    Block Diagram -- SLIMbus Host IP V2.0
  • SLIMbus Device IP Core
    • The SLIMbus v2.0 Device Controller IP is designed to provide MIPI SLIMbus compliant connectivity for a peripheral device, like an audio codec, to a SLIMbus compliant host, like an Applications Processor on a mobile platform, and share the bus bandwidth with other SLIMbus devices that may exist.
    Block Diagram -- SLIMbus Device IP Core
  • RFFE Slave IP Core
    • Compliant with MIPI’s RFFE specification Rev 3.0
    • Small silicon footprint
    • Scalable Implementation
    • Up to 15 Devices can be connected per Bus
    • Low pin count on Interface side (SCLK and SDATA)
    Block Diagram -- RFFE Slave IP Core
  • RFFE Master IP Core
    • Compliant with MIPI RFFE Specification 3.0
    • Delivered in Reuse Methodology Manual (RMM) compliant Verilog RTL format
    • Optionally delivered as a physical design
    • Small footprint
    Block Diagram -- RFFE Master IP Core
  • PCIe End Point IP Core
    • The PCI Express End Point is a high-speed, high-performance, and low-power IP core that is fully compliant to the PCI Express Specification 1.1 and 2.0.
    • The IP core is designed for applications in computing, networking, storage, servers, wireless, and consumer electronics.
    Block Diagram -- PCIe End Point IP Core
  • MIPI UniPro Software Stack
    • The MIPI Alliance was created to define and promote open standards for interfaces to mobile application processors. The UniPro (Unified Protocol) is one in a family of standard addressing the mobile market. UniPro is a high speed interface technology for interconnecting integrated circuits in mobile phones or compatible products. The targeted scenario for UniPro technology is to connect chips (such as application processor to a peripheral device) within a mobile terminal.
    • The Arasan UniPro software stack serves as a path for applications to transmit data over the hardware stack and also to indicate the availability of data from the remote host. The stack exports a generic set of device operation APIs (such as initialization, configuration, data transfer, callback registration for event notifications, shutdown etc.) for easy integration with client applications. It provides an easy-to-use interface to client application by managing all the nitty-gritty details of UniPro protocol in the stack itself. A layered architecture for the stack makes it possible to port, configure and expand to various platforms, OS and various target hardware devices.
    • The UniPro software stack implements a scheduling engine and connection specific input output queue to provide better memory utilization and to provide Quality of Service (QoS) for different requirements of the stream. Hardware does the physical bus arbitration and scheduling of packets for TC0 and TC1 traffic classes at physical level. The software does the scheduling mapping at more granular reason based on requirements of a stream.
    Block Diagram -- MIPI UniPro Software Stack
  • MIPI SoundWire Slave Controller 1.2
    • MIPI SoundWire®Slave Controller, typically integrated into audio DSP/Codecs or directly into audio peripherals such as Microphones and Amplifiers used in smart phones, tablets and mobile PCs. 
    • The IP when integrated provides SoundWire, a new audio interface to connect to Master typically embedded in Application Processor or Audio Codecs.
    Block Diagram -- MIPI SoundWire Slave Controller 1.2
  • MIPI SoundWire Master Controller 1.2
    • Compliant with MIPI SoundWire specification version 1.2
    • Configurable number of Data Ports Configurable Direction – Source or Sink
    • Implements clock gearbox with programmable frequency divider
    • Implements SoundWire Bus Clock Stop and WakeUp detection
    Block Diagram -- MIPI SoundWire Master Controller 1.2
×
Semiconductor IP