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ONFI IP

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The ONFI IP cores are used to access the external NAND flash for high speed transactions of multiple pages of read or write data taking advantage of the pipeline performance of newer enterprise NAND flash devices.

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Compare 4 ONFI IP from 4 vendors (1 - 4)
  • Nand Flash Controller
    • Simple streaming interface towards user logic for data read and write
    • Commands supported towards NAND Flash Memory:
    • ECC Logic: Hamming code used to correct 1-bit error and detect 2-bit errors
    • Commands supported from user: Block Erase, Read, Program and Copy-Back Program
    Block Diagram -- Nand Flash Controller
  • ONFI Flash Controller
    • AXI System Interface
    • NAND Flash
    Block Diagram -- ONFI Flash Controller
  • Universal NandFlash Controller
    • The Universal NAND Flash Controller (IPM-UNFC) IP core is designed specifically to enable commodity Flash memory to be effectively used in enterprise storage applications requiring high reliability and large interconnect bandwidth.
    • Using the pre-validated IPM-UNFC IP allows greatly reduced time-to-market for storage OEMs desiring higher IOPS benefitting from lower cost SLC, MLC , TLC & QLC NandFlash memory.
    Block Diagram -- Universal NandFlash Controller
  • Advanced Flash Controller Interface Core
    • Multi-Port Architecture allows connecting up to 32 NAND devices (128 total NAND targets)
    • Separate Administrative and I/O queues for flexible datapath management
    • Maximum of 1 register write per command submission/ completion
    • Industry standard bus interface (AXI-4) master used for command fetching, command completion, and data movement
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Semiconductor IP