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UCIe IP

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The UCIe™ physical layer includes the link initialization, training, power management states, lane mapping, lane reversal, and scrambling. The UCIe™ controller includes the die-to-die adapter layer and the protocol layer. The adapter layer ensures reliable transfer through link state management and parameter negotiation of the protocol and flit formats. The UCIe™ architecture supports multiple standard protocols such as PCIe, CXL and streaming raw mode.

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Search (44)
Compare 44 UCIe IP from 13 vendors (1 - 10)
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • UCIe Die-to-Die Controller IP
    • High Configurability and Customizability
    • Comprehensive Verification
    Block Diagram -- UCIe Die-to-Die Controller IP
  • 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
  • Universal Chiplet Interconnect Express (UCIe™) PHY
    • Supports up to 32Gbps per pin including 4/8/12/16/24Gbps
    • Forwarded clock, track, and valid pins
    • Sideband messaging for link training and parameter exchange
    • KGD (Known Good Die) testing capability
    • Redundant lane repair (advanced)
    • Width degradation (standard)
    • Lane reversal
    Block Diagram -- Universal Chiplet Interconnect Express (UCIe™) PHY
  • Universal Chiplet Interconnect Express (UCIe™) Controller
    • Lowest latency controller for data intensive die-to-die applications
    • Supports single and multiple PHY modules
    • CXS, CHI C2C, AXI, PCIe, CXL, and streaming protocols
    • CRC and retry mechanism
    • Sideband messaging for link training, parameter exchange, and vendor defined messages
    • Link State Management
    • Parameter Negotiation
    Block Diagram -- Universal Chiplet Interconnect Express (UCIe™) Controller
  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe Verification IP
    • Available in native SystemVerilog (UVM/OVM /VMM) and Verilog.
    • Unique development methodology to ensure highest levels of quality.
    • Availability of various Regression Test Suites.
    • 24X5 customer support.
    Block Diagram -- UCIe Verification IP
  • UCIe 2.0 Verification IP
    • Available in native SystemVerilog (UVM/OVM /VMM) and Verilog.
    • Unique development methodology to ensure highest levels of quality.
    • Availability of various Regression Test Suites.
    • 24X5 customer support.
    Block Diagram -- UCIe 2.0 Verification IP
  • UCIe and BOW Universal PHY
    • Novel Redundancy for Hi-Rel,
    • Support for 16&18-bit wide data,
    • Support Synchronous Operation,
    • Supports Advanced packaging,
    Block Diagram -- UCIe and BOW Universal PHY
  • D2D UCIe 1.1
    • Compatible with UCIe v1.1 specification
    • Features single-ended, source-synchronous, and DDR I/O signaling
    • Supports 32-bit (16-bits TX + 16-bit RX) data bus per module for standard packages
    • Offers a high clock frequency up to 16GHz
    Block Diagram -- D2D UCIe 1.1
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