I/O Library IP

A 1.8V/3.3V flip-chip I/O library with ESD-immune GPIOs and integrated POC circuitry in TSMC FFC/FFC+.
This library is a production-ready I/O library built on the TSMC 12nm process. The library features 1.8V to 3.3V GPIOs with programmable drive strength, hysteresis, and control logic.

KA16UGLVDS01ST001 is a LVDS IO handling data rate up to 50Mbps with a maximum loading of 60pF.
The differential voltage swing can be programmable from 0.35V to 1V.
The output enable control function can be activated to decide the IO as input/output function. This IP also includes the IO PAD.

Silicon proven with maximum speed @1.5Gbps per lane
Suitable for Automotive applications with ESD levels: HBM > 4KV and CDM > 750V
LVDS TX PHY: 4-data lanes plus 1-clock lane with each lane can be individually turned off
Supports long-distance transmission: Capable of maintaining signal integrity over longer cable length

The SD 3.0 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds.
The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead.

The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.

The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels.
The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components.

The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI^® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard.
The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI).

The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI^® Alliance Standard for D-PHY and a high performance 4-channel LVDS Serializer implemented using digital CMOS technology.
In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.

Library contains approx. 60 IO cells
Support for all metal-stacks of 22FDX®
Low voltage cells with nominal core voltages down to 0.4 V for glue-less interfacing to ULV Racyics® ABX digital standard cell domains
Low leakage cells for ultra low power always-on domain usage

A Flipchip I/O Library with dynamitcally switchable 1.8V/3.3V GPIO, 5V I2C/SM- Bus ODIO, 5V OTP Cell, 1.8V & 3.3V Analog Cells and associated ESD.
A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.