IP Catalog > Security IP > Other

Other

All offers in Other
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (22)
Compare 22 Other from 11 vendors (1 - 10)
  • Ultra-Compact 3GPP Cipher Core
    • Keystream generation using the ZUC Algorithm version 1.6 (ZUC-2011)
    • High throughput: up to 40 Gbps in 65 nm process, 10 Gbps in Altera Stratix III
    • Small size: from 7.5K ASIC gates
    • Satisfies ETSI SAGE ZUC and EAE3/EIA3 specifications
    Block Diagram -- Ultra-Compact 3GPP Cipher Core
  • LZRW3 Data Compression Core
    • The Helion LZRW3 core implements the LZRW3 data compression algorithm in Altera FPGA without the need for external memory storage.
    • It is capable of handling data throughputs in excess of 1 Gigabit/sec, and is ideal for use for improving system performance and efficiency in data communications, networking and data storage applications.
    Block Diagram -- LZRW3 Data Compression Core
  • External NAND flash protection, designed to secure stored assets with a local key from PUF
    • PUFenc is designed to protect external flash memory and its stored assets.
    • The IP provides asset encryption, such as a learning model for AI or firmware for the chip with a local key from the PUF.
    • It adds an additional layer of security by avoiding using the global key, which is a shared key among ICs after the chip leaves the manufacturing floor.
    Block Diagram -- External NAND flash protection, designed to secure stored assets with a local key from PUF
  • Via-PUF Security Chip for Root of Trust

    • The vPUF® IP, powered by Via PUF (Physically Unclonable Function) technology, provides a unique silicon fingerprint for inborn identity function, essential for the Root of Trust in security applications

    Block Diagram -- Via-PUF Security Chip for Root of Trust
  • PUF Security
    • A physical unclonable function, or PUF, is a "digital fingerprint" that serves as a unique identity for a semiconductor device such as a microprocessor
    • PUFs are based on physical variations which occur naturally during semiconductor manufacturing, which makes it possible to differentiate between otherwise identical semiconductors
    • The PUF IP consists of PUF array and control logic
    Block Diagram -- PUF Security
  • Fully Digital Physically Unclonable Function (PUF) - PQC Ready
    • Secure storage without the use of any non volatile memory
    • No external key provisioning required
    • Does not require costly SRAM blocks
    • Proven reliability regarding voltage, temperature and aging with error probability much lower than 10-9
    Block Diagram -- Fully Digital Physically Unclonable Function (PUF) - PQC Ready
  • High-Performance Lossless Compression/Encryption Combo Core
    • Each frame is compressed and decompressed independently
    • Compatibility with public-domain LZ software implementations allows for interoperability
    • Parameterizable maximum block size (up to 16 megabytes)
    • Support for compression and decompression in a single core; dedicates compression and decompression versions are available
    Block Diagram -- High-Performance Lossless Compression/Encryption Combo Core
  • RC4 Keystream Generator
    • Keystream generation using the RC4 algorithm
    • Small size: from 20K ASIC gates
    • Satisfies the ARC4 specification
    • Capability to save and restore internal state using a data bus with parameterized width.
    Block Diagram -- RC4 Keystream Generator
  • Digital PUF IP
    • Generate unclonable 128 or 256-bit seeds with a compact, logic-based PUF that drops into any SoC.
    • Digital PUF IP adds true hardware identity for secure boot, key generation, and device authentication with minimal silicon overhead.
  • PUF IP
    • Secure provisioning
    • Secured identities
    • High entropy seeds
    • Built-in resistance to side channel attacks
×
Semiconductor IP