PCIe 7.0 IP
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9
IP
from 3 vendors
(1
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9)
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PCIe 7.0 Controller with AXI
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Scalable data path
- Advanced PIPE modes and port bifurcation
- Supports multiple virtual channels (VCs) in FLIT and non-FLIT modes
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PCIe 7.0 Switch
- Configurable from PCIe 7.0 x8/ PCIe6x16 @1GHz clock down to PCIe 5.0 x1
- Highly scalable with up to 31 configurable external or embedded endpoints
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PCIe 7.0 Retimer Controller
- Supports PCIe 7.0 128 GT/s speeds at up to x16 lanes
- CXL 3.0 aware
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PCIe 7.0 Controller
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/
- completion traffic
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PCIe 7.0 PHY in TSMC (N5, N3P)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SSC)
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PCIe 7.0 Integrity and Data Encryption (IDE) Security IP Module
- Full support of PCI Express 7.0 (64GT/s) IDE specification
- High-performance AES-GCM based packet encryption, decryption, authentication
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PCIe 7.0 Controller (can be configured to support EP, RP, DM, or SW applications)
- Supports all required features of the PCI Express 7.0, 6.x, 5.0, 4.0, 3.1, 2.1, and 1.1 specifications
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PCIe 7.0 PHY IP
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 7.0, encoding, backchannel initialization
- Lane margining at the receiver
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Ethernet Real-Time Publish-Subscribe (RTPS) IP Core
- OMG DDSI-RTPS 2.2 compliant interface with hardware-based offload
- Hardware DMA engines with message label mapped buffers
- Message label validation and filtering
- Host processor offloaded from all networking responsibilities
