IP for VIS

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Compare 91 IP for VIS from 3 vendors (1 - 10)
  • USB 3.1 Cable Marker IP
    • USB PD 3.1 compliant.
    • Single chip solution – just two external capacitors.
    • 4 pin package.
    • Less than 1mm2 area in 180nm.
    • PROM programmed through vendor message protocol.
    • Based on Obsidian’s mature PD technology.
    • Integrated PROM enables customized response to a wide range of vendor requirements.
    • Active Ra pulls down only requires 10uA at 5V., but is <1K below 2V.
    • Power <5mW. Enabled by CC data activity. I.e. very low duty cycle.
    • Programming can be done after assembly into the cable. Fuse lock function.
    • Supports low cost, 4 layer PCB assembly.
    Block Diagram -- USB 3.1 Cable Marker IP
  • Complete USB Type-C Power Delivery IP
    • Mixed signal Analog Front End Macros for 65n, 130n, 150nm, and 180n technologies.
    • RTL code from AFE to I2C compatible register set.
    • Stand alone C code for Protocol, Device Policy Manager, and System Policy Manager.
    • IP demonstration & development board, with compliance reports. 
    • Full chip integration of USB Type-C, and associated software.
    Block Diagram -- Complete USB Type-C Power Delivery  IP
  • 32KHz Low Power Oscillator
    • 850nW typical power @32KHz.
    • Available frequencies 10KHz – 100KHz.
    • No external components.
    • 60ppm/°C temperature sensitivity.
    • 0.3%/100mV vdd sensitivity.
    • Base cell area 0.005mm2.
    Block Diagram -- 32KHz Low Power Oscillator
  • General Purpose PLL for VIS 150nm
    • Wide range N, M, P integer dividers.
    • 40MHz – 600MHz output frequency range.
    • Comparable frequency range 8MHz – 50MHz.
    • 18pS RMS cycle to cycle jitter at 600MHz.
    • Lock-detect function.
    • Bypass function.
    Block Diagram -- General Purpose PLL for VIS 150nm
  • VIS 150nm 5V Bandgap voltage reference
    • 2.5V-5.5V operation.
    • 3σ 4% untrimmed voltage reference accuracy.
    • 2% variation over -40ºC to 125ºC after trimming.
    • 70dB low frequency PSRR.
    • Trimmed, temperature compensated, 10µA reference current outputs with 3% accuracy.
    • Trimmed IPTAT output currents can be provided.
    Block Diagram -- VIS 150nm 5V Bandgap voltage reference
  • 8Kx8 Bits OTP (One-Time Programmable) IP, VIS 0.15µm 1.8V/5V BCD GIII Process
    • Small IP size, 1P4M (M1+3Mx)
    • Low program voltage/current
    • Low read voltage/current
  • Embedded OTP (One-Time Programmable) IP, 512x12 bits for 1.5V/7V/32V HV
    • Logic Embedded IP
    • Programming NeoFuse cell by using quantum tunneling mechanism
    • High yield performance
    • Small IP size
  • Embedded OTP (One-Time Programmable) IP, 512x12 bits for 1.5V/7V/32V HV
    • Logic Embedded IP
    • Programming NeoFuse cell by using quantum tunneling mechanism
    • High yield performance
    • Small IP size
  • Embedded EEPROM IP, 32x16 bits for 1.8V/3.3V Logic
    • Logic Embedded IP
    • Programming with FN program, erasing with FN erase
    • High yield performance
    • Small IP size
  • Embedded EEPROM IP, 1Kx8 bits for 3.3V/18V HV
    • Logic Embedded IP
    • Programming with FN program, erasing with FN erase
    • High yield performance
    • Small IP size
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