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Security Processor IP

Security Processor IP cores support advanced security features such as encryption, decryption, authentication, and secure boot, safeguarding devices against cyber threats and unauthorized access. Ideal for applications in IoT, automotive, mobile devices, and financial systems, Security Processor IP cores help developers integrate trusted, high-performance security capabilities into their designs.

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Search (19)
Compare 19 Security Processor IP from 10 vendors (1 - 10)
  • Crypto Coprocessor
    • Comprehensively support all CPU architectures 
    • Crypto engine collective, consisting of private key cipher, message authentication code, hash, and  key derivation functions that are NIST CAVP certified and OSCCA standards compliant 
    • Key wrapping function aiding the export of keys for external use 
    Block Diagram -- Crypto Coprocessor
  • Compact Processor for Security
    • Secure MPU against memory tampering
    • Shields against side-channel attack
    • Secure debug for multi-party software development
    • Flexible configurations and run-time control
    Block Diagram -- Compact Processor for Security
  • SoC Security Platform / Hardware Root of Trust
    • GEON-SoC is an area-efficient, processor-agnostic, hardware root of trust for SoC designs.
    • It implements secure boot and can optionally be enhanced to support firmware decryption and secure debug, or to act as a post-boot hardware security module (HSM).
    Block Diagram -- SoC Security Platform / Hardware Root of Trust
  • ARC EM22FS safety processor
    • Dual-core lockstep safety processor supports ISO 26262 automotive safety standards
    • Single solution support for safety level up to ASIL D; Supports both ASIL D lockstep operation or ASIL B single core operation
    • Includes hardware safety features such as ECC, integrated user-programmable windowed watchdog timer, and lockstep safety monitor
    Block Diagram -- ARC EM22FS safety processor
  • ARC SEM120D Security Processor with DSP for Low Power Embedded Applications
    • Performance-, power- and area-efficient security processors for embedded applications
    • Secure privilege mode orthogonal to kernel/user mode
    • Enhanced secure MPU with context ID for secure or normal operation
    • Up to 16 configurable protected regions and per region scrambling capability
    Block Diagram -- ARC SEM120D Security Processor with DSP for Low Power Embedded Applications
  • ARC SEM110 Security Processor for Low Power Embedded Applications
    • Performance-, power- and area-efficient security processors for embedded applications
    • Secure privilege mode orthogonal to kernel/user mode
    • Enhanced secure MPU with context ID for secure or normal operation
    • Up to 16 configurable protected regions and per region scrambling capability
    Block Diagram -- ARC SEM110 Security Processor for Low Power Embedded Applications
  • ARC SEM130FS Safety and Security Processor
    • ASIL D compliant dual-core, lockstep safety processor supports ISO 26262 automotive safety standards and provides advanced security to protect against evolving threats
    • Secure privilege mode orthogonal to kernel/user mode
    • Integrated self-checking safety monitor capable of time diversity
    • Uniform instruction timing and timing/ power randomization for side channel resistance
    Block Diagram -- ARC SEM130FS Safety and Security Processor
  • ARC-V RMX-100 Processor IP
    • Family of 32-bit RISC processors for ultra-low power embedded applications
    • Based on the RISC-V ISA, leveraging standard 32-bit protocols (and extensions)
    • DSP instruction extensions (RMX-100D)
    • Easy DSP programming support with MetaWare C/C++ Compiler (RMX-100D)
    Block Diagram -- ARC-V RMX-100 Processor IP
  • ARC-V RMX-500 Processor IP
    • Family of 32-bit processors for low-power embedded applications
    • Based on the RISC-V ISA, leveraging standard 32-bit protocols (and extensions)
    • RISC and RISC + DSP 32-bit processors for low-power embedded applications (RMX-500D)
    • DSP instruction extensions (RMX-500D)
    Block Diagram -- ARC-V RMX-500 Processor IP
  • ARC-V RMX Series Functional Safety Processor IP
    • Developed for full ASIL D compliance (systematic and random faults)
    • Tightly-coupled dual-core safety implementation based on ultra-compact ARC-V RMX processors
    • Single solution support for safety level up to ASIL D; Supports both ASIL D lockstep operation or ASIL B single-core operation (RMX-510-FS only)
    • Integrated hardware safety features including ECC, user-programmable windowed watchdog timer, end-to-end protection (E2E) for buses/data-path, and lockstep safety monitor
    Block Diagram -- ARC-V RMX Series Functional Safety Processor IP
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