IP Catalog > Wireless IP Cores

Wireless IP Cores

Wireless IP cores are specialized hardware modules designed to provide efficient and reliable wireless communication capabilities for a wide range of applications. These cores enable the integration of wireless standards such as Wi-Fi, Bluetooth, Zigbee, LTE, and 5G into embedded systems and devices, streamlining the development of connected solutions.

Explore our vast directory of Wireless IP cores below.

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Search (322)
Compare 322 Wireless IP Cores from 76 vendors (1 - 10)
  • WIFI 2.4G/5G Low Power Wakeup Radio IP
    • Dual-band Wi-Fi IP with a low-power wakeup radio, aimed at energy-efficient, always-on connectivity.
    Block Diagram -- WIFI 2.4G/5G Low Power Wakeup Radio IP
  • Radar IP
    • High-resolution radar IP for accurate object detection and tracking.
    Block Diagram -- Radar IP
  • WIFI 11AX IoT IP
    • Energy-efficient Wi-Fi 6 (802.11ax) IoT IP designed for high-speed, reliable smart device connectivity.
    Block Diagram -- WIFI 11AX IoT IP
  • WIFI 11AX IP
    • High-performance Wi-Fi 6 (802.11ax) IP for enhanced, efficient wireless connectivity.
    Block Diagram -- WIFI 11AX IP
  • LTE IP
    • Scalable and robust LTE IP for seamless 4G wireless communications integration.
    Block Diagram -- LTE IP
  • GPS IP
    • Low-power, high-accuracy GPS IP designed for precise positioning and navigation.
    Block Diagram -- GPS IP
  • PTP/gPTP Verification IP
    • Provides Ethernet fully compliant to 802.3-2018 supporting all media independent interfaces for (1/10/25/40/50/100/200/400/800 G)
    • Provides PTP as per IEEE 1588-2008 specification
      • Supports BMCA
      • Supports PTP Delay Request Mechanism (Announce-sync-FollowUp-DelayReq-DelayResp)
      • Supports PTP Peer Delay Mechanism (PdelayReq – PdelayResp - PdelayRespFollowUp)
      • Supports Local Clock generation with user configurable start for timestamp generation
      • Supports Master-Slave and slave only port state machines capable with support for all message timers
      • Supports basic Management Messages with user control from test/sequence
      • Supports one step and two step clock timestamping
    • Supports BMCA
    • Supports PTP Delay Request Mechanism (Announce-sync-FollowUp-DelayReq-DelayResp)
    Block Diagram -- PTP/gPTP Verification IP
  • DVBS2
    •  A flexible input stream adapter, suitable for operation with single and multiple input streams of various formats (packetized or    continuous)
    •  A powerful FEC system based on low-density parity check (LDPC) codes concatenated with BCH codes, allowing quasi-error-free    operation at approx. 0.7 dB to 1 dB from the Shannon limit, depending on the transmission mode
    Block Diagram -- DVBS2
  • ORAN Verification IP
    • Compliant with ORAN Specification V6.0.
    • Complete ORAN Tx/Rx functionality.
    • Supports O-RU and O-DU
    • Supports the below encapsulation
    Block Diagram -- ORAN Verification IP
  • LDPC Decoder for 5G NR and Wireless
    • The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance.
    • It employs the Min-Sum LDPC decoding algorithm to ensure efficient decoding.
    • The core allows for programmable internal bit widths at compile time, though the default values are usually sufficient.
    Block Diagram -- LDPC Decoder for 5G NR and Wireless
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