Wireless IP Cores

The CMS0005 802.16 Channel Codec provides all of the functionality necessary to implement the back end data processing in an 802.16a WirelessMAN-OFDM Phy Layer device.
Its design has been carefully constructed to provide excellent FPGA performance without compromising the ASIC implementation in terms of area or speed.

The Commsonic CMS0070 ISDB-S3 Modulator with integrated LDPC encoder has been designed specifically to address the requirements of the ARIB STD-B44 advanced wide-band digital satellite standard.
The core provides all the necessary processing steps to modulate a single transport stream (or baseband frame) into a complex I/Q signal for input to a pair of DACs, or an interpolating DAC device such as the AD9857(or AD9957). Optionally, the output can be selected as an IF to supply a signal DAC.

The CMS0071 ISDB-S3 Demodulator is a high-performance (A)PSK demodulator core intended for ARIB STD-B44 ISDB-S3 advanced wide band digital satellite standard.
Operating symbol rate is programmed from a register and extends from approximately 40% of the master clock frequency down to an arbitrary low rate that is set through synthesis options. The range would normally be dictated by the application and, in particular, the phase noise characteristics of the radio system.

The CMS0033 ATSC 8-VSB Modulator with integrated Channel Coder has been designed specifically to implement the 8-VSB requirements of the ATSC Digital Television Standard (A/53).
The core provides all the necessary processing steps to modulate a single transport stream into a complex I/Q signal for input to a pair of DACs, or a DDS up-conversion DAC such as the AD9857(or AD9957). Optionally, the output can be selected as an IF to supply a signal DAC.

These high performance cores have been designed to provide hardware acceleration of the underlying 802.11 WPA security algorithms, which in combination with the Helion AES-CCM core family, may be used to implement a full 802.11i WPA24 security solution very efficiently in Xilinx FPGA.
The security processing is split into two parts, since they are likely to be required at different points within the MAC subsystem.

Fully compliant with Bluetooth Specifications Ver 1.1 as specified by Special Interest Group (SIG).
Compliance to Test Suites as provided Standard Sample Test from Bluetooth Qualification Body (BQB).
Reduced Area by logical sharing thereby Low Power Consumption.
Time Division Duplex (TDD).

The MAC core for Wireless LAN is compatible with 802.11 a b and g IEEE Standards.
It is designed to handle packetized DSSS (Direct Sequence Spread Spectrum) and OFDM (Orthogonal Frequency Division Multiplexing) data transmissions; the software implementation supports all data rates.
The MAC management or control functionality is implemented in firmware while the time critical functionality is implemented in hardware.

The Extensible Radio Access Network (O-RAN WG4 Fronthaul Interface) defines a fronthaul interface between a lower-layer split distributed unit (DU) and remote unit (RU) in an Evolved Universal Terrestrial Access Network (E-UTRAN) and Next-Generation Radio Access Network (NG-RAN) system with a lower layer functional split-7-2x based architecture
The O-RAN IP implements control and user plane protocol specified in O-RAN-FH.CUS.0-v03.00.

Forward-error correction (FEC) channel codes commonly improve the energy efﬁciency of wireless communication systems
Turbo codes are suitable for 3G and 4G mobile communications and satellite communications
You can use Turbo codes in other applications that require reliable information transfer over bandwidth- or latency-constrained communication links in the presence of data-corrupting noise. The 4G Turbo-V Intel® FPGA IP comprises a downlink and uplink accelerator for vRAN and includes the Turbo Intel® FPGA IP.

Dual-band Wi-Fi IP with a low-power wakeup radio, aimed at energy-efficient, always-on connectivity.