Wireless IP Cores

Wireless IP cores are specialized hardware modules designed to provide efficient and reliable wireless communication capabilities for a wide range of applications. These cores enable the integration of wireless standards such as Wi-Fi, Bluetooth, Zigbee, LTE, and 5G into embedded systems and devices, streamlining the development of connected solutions.

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Compare 316 Wireless IP Cores from 75 vendors (1 - 10)
  • PTP/gPTP Verification IP
    • Provides Ethernet fully compliant to 802.3-2018 supporting all media independent interfaces for (1/10/25/40/50/100/200/400/800 G)
    • Provides PTP as per IEEE 1588-2008 specification
      • Supports BMCA
      • Supports PTP Delay Request Mechanism (Announce-sync-FollowUp-DelayReq-DelayResp)
      • Supports PTP Peer Delay Mechanism (PdelayReq – PdelayResp - PdelayRespFollowUp)
      • Supports Local Clock generation with user configurable start for timestamp generation
      • Supports Master-Slave and slave only port state machines capable with support for all message timers
      • Supports basic Management Messages with user control from test/sequence
      • Supports one step and two step clock timestamping
    • Supports BMCA
    • Supports PTP Delay Request Mechanism (Announce-sync-FollowUp-DelayReq-DelayResp)
    Block Diagram -- PTP/gPTP Verification IP
  • DVBS2
    •  A flexible input stream adapter, suitable for operation with single and multiple input streams of various formats (packetized or    continuous)
    •  A powerful FEC system based on low-density parity check (LDPC) codes concatenated with BCH codes, allowing quasi-error-free    operation at approx. 0.7 dB to 1 dB from the Shannon limit, depending on the transmission mode
    Block Diagram -- DVBS2
  • ORAN Verification IP
    • Compliant with ORAN Specification V6.0.
    • Complete ORAN Tx/Rx functionality.
    • Supports O-RU and O-DU
    • Supports the below encapsulation
    Block Diagram -- ORAN Verification IP
  • LDPC Decoder for 5G NR and Wireless
    • The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance.
    • It employs the Min-Sum LDPC decoding algorithm to ensure efficient decoding.
    • The core allows for programmable internal bit widths at compile time, though the default values are usually sufficient.
    Block Diagram -- LDPC Decoder for 5G NR and Wireless
  • Ultra-low-power 2.4 GHz transceiver for Bluetooth 5.3, 802.15.4 and IoT
    • The icyTRX ultra-low-power RF transceiver is designed to meet standards such as Bluetooth Low Energy (BLE), 802.15.4 PHY Layer (e.g. ZigBee), and proprietary standards with data rates from 62.5 kBit/s up to 4 Mbit/s.
    • icyTRX offers 5.3 mW consumption in receive mode from a 1.0 V supply. icyTRX is a complete transceiver that is designed for miniaturization, yielding an area of analog RF of less than 1 mm2 in 55 nm CMOS, requiring minimal external components thanks to high degree of integration. icyTRX is designed for easy integration into ASICs and SoCs.
    Block Diagram -- Ultra-low-power 2.4 GHz transceiver for Bluetooth 5.3, 802.15.4 and IoT
  • Bluetooth 5.3 Dual Mode PHY IP
    • The icyTRX-DM ultra-low-power RF transceiver IP is designed to meet 2.4 GHz standards like Bluetooth Classic (BR/EDR), Bluetooth Low Energy (BLE), 802.15.4 PHY Layer (e.g. ZigBee), and proprietary standards.
    • icyTRX-DM IP targets by far the lowest power consumption together with state-of-the-art performances (sensitivity, interferers rejection) and with minimal cost.
    • Thanks to its built-in LDOs, its fully programmable modem and its interface compatible with leading BT baseband controllers, the icyTRX-DM IP is optimized for easy integration into ASICs and SoCs
    Block Diagram -- Bluetooth 5.3 Dual Mode PHY IP
  • NFC Tag IP for Proximity Integrated Circuit Cards (PICC) and Vicinity Integrated Circuit Cards (VICC)
    • Our state-of-the-art NFC tag IP integrates seamlessly with ISO 14443-A, 14443-B, and 15693 standards.
    • Ideal for both battery-less and battery-operated devices, this technology ensures best-in-class performance and versatility.
    Block Diagram -- NFC Tag IP for Proximity Integrated Circuit Cards (PICC) and  Vicinity Integrated Circuit Cards (VICC)
  • 5G RAN DSP
    • The XC23 is the most powerful DSP core available today for communications applications. The-XC23 offers scalable architecture and dual thread design with support for AI, addressing growing demand for smarter, more efficient wireless infrastructure
    • Targeted for 5G and 5G-Advanced workloads, the XC23 has two independent execution threads and a dynamic scheduled vector-processor, providing not only unprecedented processing power but unprecedented utilization on real-world 5G multitasking workloads.
    Block Diagram -- 5G RAN DSP
  • 5G IoT DSP
    • The XC21 is the most efficient vector DSP core available today for communications applications.
    • The XC21 DSP is designed for low-power, cost- and size-optimized cellular IoT modems, NTN VSAT terminals, eMBB and uRLLC applications.
    • Ceva-XC21 offers scalable architecture and dual thread design with support for AI, addressing growing demand for smarter, yet more cost and power efficient cellular devices
    Block Diagram -- 5G IoT DSP
  • Open RAN Platform for Base Station and Radio
    • The Ceva-PentaG RAN platform is a modular, optimized hardware and software IP for implementing L1 PHY baseband processing in 5G base station and other cellular infrastructure SoCs.
    • Employing Ceva’s highest-performance DSP cores and dedicated hardware accelerators teamed with optimized software, the Ceva-PentaG RAN platform is in use by 5G industry incumbents, and can substantially reduce development time and risk for new entrants.
    Block Diagram -- Open RAN Platform for Base Station and Radio
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