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Coprocessor IP

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Compare 50 Coprocessor IP from 11 vendors (1 - 10)
  • Radar processing IP suite for Advanced Driver Assistance Systems
    • The eSi-ADAS™ is a suite of radar accelerator IP including a complete Radar co-processor engine, they enhance the overall performance and capabilities of radar  systems for automotive, drone and UAV applications that require fast and responsive situational awareness.
    • The IP has been licensed to some of the leading automotive Tier 1 and Tier 2 suppliers and is in production vehicles.
    Block Diagram -- Radar processing IP suite for Advanced Driver Assistance Systems
  • BitBLT Graphics Hardware Accelerator (AXI Bus)
    • The DB9100AXI BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to combining existing bitmaps on and off-screen using one of 256 Raster Operations.
    • A Raster Operation (ROP) is a bitwise Boolean operation (such as AND, OR, XOR, NOT).
    • The DB9100AXI also contains a Monochrome Bitmap Color Expansion feature, typically used for font expansion of compressed character bitmaps. A 1-bit depth bitmap is expanded to one of two colors, a foreground or background color, with the foreground color representing the text, and the background color the non-text background.
    Block Diagram -- BitBLT Graphics Hardware Accelerator (AXI Bus)
  • NPU IP for Data Center and Automotive
    • 128-bit vector processing unit (shader + ext)
    • OpenCL 1.2 shader instruction set
    • Enhanced vision instruction set (EVIS)
    • INT 8/16/32b, Float 16/32b in PPU
    • Convolution layers
    Block Diagram -- NPU IP for Data Center and Automotive
  • NPU IP for AI Vision and AI Voice
    • 128-bit vector processing unit (shader + ext)
    • OpenCL 3.0 shader instruction set
    • Enhanced vision instruction set (EVIS)
    • INT 8/16/32b, Float 16/32b
    Block Diagram -- NPU IP for AI Vision and AI Voice
  • 16 bit DSP fixed point coprocessor
    • The APS DSP has been designed from the ground up as a companion to the APS family of processors, ensuring simple integration into your embedded system.
    • The additional instructions are fully integrated with the assembler and simple macros make using the DSP from C or C++ very simple.
    Block Diagram -- 16 bit DSP fixed point coprocessor
  • Pulse Per Second (PPS) Clock to PPS core
    • Configurable input frequency from 100Hz to 100MHz
    • Input frequency supervision
    • PPS duty cycle configurable in ms steps
    • PPS Generation runs directly on Input Clock (minimal Jitter)
    Block Diagram -- Pulse Per Second (PPS) Clock to PPS core
  • Time aligned Frequency Generator core
    • Configurable frequency signal generation (0-10MHz) in 1Hz steps
    • Configurable polarity
    • Output delay compensation
    Block Diagram -- Time aligned Frequency Generator core
  • ComputeRAM
    • Available as a 18 kB macro in GlobalFoundries 22FDX process; - Memory Compiler and FinFET variants under development
    • Low power sleep mode with data retention
    • Built using proven foundry SRAM bit cells, fully CMOS, strictly obeys foundry DFM/DRC rules
    • Bit-accurate computation
    Block Diagram -- ComputeRAM
  • Network Redundancy (HSR & PRP) core
    • Supports the HSR and PRP redundancy protocol according to IEC62439-3 rev 3
    Block Diagram -- Network Redundancy (HSR & PRP) core
  • Radio Clock (DCF77) Master core
    • DCF MasterClock
    • Supports DCF-77 format
    • DCF encoding and time format conversion
    Block Diagram -- Radio Clock (DCF77) Master core
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