PCIe 7.0 Controller with AXI

Overview

Key Features

• Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
• Scalable data path
• Advanced PIPE modes and port bifurcation
• Supports multiple virtual channels (VCs) in FLIT and non-FLIT modes
• Supports Endpoint, Root-Port, Lite (Subordinate/Manager)
• PCIe to AXI and AXI to PCIe Ordering Rules guarantee AXI deadlock prevention
• AXI bridge and AXI interconnect allows full performance on AXI interfaces
• Each AMBA AXI user interface can be configured independently from 64-bit to 1024-bit and with independent clock speeds to provide a variety of connectivity options
• Advanced RAS features
• Optional IDE security with AES-GCM encryption, decryption and authentication

Block Diagram

Deliverables

• IP Files
  • Verilog RTL source code
  • Libraries for functional simulation
  • Configuration assistant GUI (Wizard)
• Full Documentation
• Reference Designs
  • Synthesizable Verilog RTL source code
  • Simulation environment and test scripts
  • Synthesis project and DC constraint files (ASIC)

Technical Specifications