The Semiconductor IP Marketplace

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The Semiconductor IP Marketplace that puts you first

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Spotlight

  • ORAN IP core
    • ORAN IP core is a highly scalable and silicon agnostic implementation of the interoperable O-RAN WG4 defined 7.2x interface for deployment in O-DU and O-RU products, targeting any ASIC, FPGA or ASSP technologies.
    • The ORAN over eCPRI implementation builds on long-time experience designing CPRI and Radio-Over-Ethernet solutions for fronthaul and delivers a flexible engine that is prepared for tight integration with software applications.
    Block Diagram -- ORAN IP core
  • E-Series GPU IP
    • E-Series GPU IP delivers fast and flexible parallel compute that scales from wearables to the cloud.
    • E-Series represents a new era of GPU IP with the introduction of a lot of dense, deeply integrated acceleration for power-efficient AI operations – up to 4x more than Imagination D-Series GPU IP.
    Block Diagram -- E-Series GPU IP
  • 4-port Receiver/Transmitter/Repeater HDCP 2.3 on HDMI 2.0 and/or DisplayPort 2.0/1.4 ESM (generation 3)
    • The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with complete and robust transmitter (TX), receiver (RX) and repeater (Rep) implementations of the HDCP 2.3 content protection technology over HDMI 2.1/2.0, DisplayPort 2.0/1.4, and USB 3.x Type-C wired connections.
    • These solutions help designers shorten development cycles and fully meet the stringent security requirements of the DCP LLC licensing authority.
  • AI IP Core
    • The low-power and high-perFormance Al IP developed by DeepMentor integrates the SOC of RISC-V. Customers can quickly integrate a unique combination oF silicon intellectual property into an Al SOC chip.
    • System manufacturers do not need to worry about the problems of Al soFtware integration and system development, and can immediately have unique AI products in the market
    Block Diagram -- AI IP Core
  • All-In-One RISC-V NPU
    • Optimized Neural Processing for Next-Generation Machine Learning with High-Efficiency and Scalable AI compute
    Block Diagram -- All-In-One RISC-V NPU
  • On-Die PDN Analyzer for Transistor-Level Visibility and Telemetry
    • The Aeonic Insight™ PDN IQ is an in-situ, on-die PDN (Power Delivery Network) analyzer providing transistorlevel PDN telemetry at nanosecond scale.
    • The telemetry provided can be applied across the silicon lifecycle to optimize power, performance, and reliability.
    • PDN IQ can be used to characterize V-F curves to develop an optimal setpoint to balance power and performance.
    Block Diagram -- On-Die PDN Analyzer for Transistor-Level Visibility and Telemetry

UCIe Controller IP View All

  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
  • UCIe PHY & D2D Adapter
    • 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S)
    • UCIe v1.1 specification
    Block Diagram -- UCIe PHY & D2D Adapter
  • 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- 2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe

PCIe 7.0 IP View All

  • PCIe 7.0 Controller with AXI
    • Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
    • Separate native TX/RX data path separating posted/Non posted/completion traffic
    • Handles up to 4 TLPs per cycle
    • Advanced PIPE modes and port bifurcation
    Block Diagram -- PCIe 7.0 Controller with AXI
  • PCIe 7.0 PHY IP
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
  • PCIe 7.0 PHY in TSMC (N5, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Supports PCIe 7.0, encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SSC)

AI IP View All

  • RISC-V CPU IP
    • RISC-V RVA23 Compliant 
    • >18 SPECint2006/GHz
    • 8-wide decode unit
    • Advanced branch predictor
    Block Diagram -- RISC-V CPU IP
  • NPU IP for Embedded ML
    • Fully programmable to efficiently execute Neural Networks, feature extraction, signal processing, audio and control code
    • Scalable performance by design to meet wide range of use cases with MAC configurations with up to 64 int8 (native 128 of 4x8) MACs per cycle
    • Future proof architecture that supports the most advanced ML data types and operators
    Block Diagram -- NPU IP for Embedded ML
  • Future-proof IP for training and inference with leading performance per watt and per dollar
    • RISC-V-based AI IP development for enhanced training and inference.
    • Silicon-proven solutions tailored for AI workload optimization.
    • Energy-efficient performance with industry-leading Perf/W.
    Block Diagram -- Future-proof IP for training and inference with leading performance per watt and per dollar

MIPI IP View All

RISC-V IP View All

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