IP for TSMC

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Compare 4,287 IP for TSMC from 107 vendors (1 - 10)
  • High Speed 16GHz PLL
    • Type II ,3rd order low jitter PLL
    • Auto calibration for process and temperature (USP)
    • Programmable frequency using CSR registers
    • 8/10/16GHz quadrature clocks
    • Operating temperature -40 to 125
    Block Diagram -- High Speed 16GHz PLL
  • Multi-constellation and Multi-frequency Correlators Soft GNSS IP for high sensitivity and high accuracy GNSS receivers
    • 64 parallel GNSS signal tracking channels with accurate and precise measurements
    • Massive and wide bandwidth correlators enable fast acquisition and high precision
    • Supports all signals in L1, L2, L5 and S band frequencies from GPS, GALILEO, GLONASS, BeiDou, QZSS, IRNSS, and SBAS constellations
    • Efficient and generic PRN code handling architecture to support future signal structures
    Block Diagram -- Multi-constellation and Multi-frequency Correlators Soft GNSS IP for high sensitivity and high accuracy GNSS receivers
  • 100G / 200G / 400G / 800G / 1.6T MACsec
    • The MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE.
    • It protects components in Ethernet networks especially very high-speed Ethernet used in cloud, data center, and backhaul networks.
    • The MACsec IP is a fully compliant solution that provides line-rate encryption and supports VLAN-in-Clear.
    Block Diagram -- 100G / 200G / 400G / 800G / 1.6T MACsec
  • 10M MACsec
    • The MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE.
    • It protects components in Ethernet networks especially very low-speed Ethernet used in automotive, industrial, and consumer applications.
    • The MACsec IP is a fully compliant solution that provides line-rate encryption and is optimized for the smallest area size.
    Block Diagram -- 10M MACsec
  • 1G/2.5G/5G/10G/25G/50G MACsec
    • The MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE.
    • It protects components in Ethernet networks especially high-speed Ethernet used in automotive, industrial, cloud, data center, and wireless infrastructure.
    • The MACsec IP is a fully compliant solution that provides line-rate encryption and supports VLAN-in-Clear.
    Block Diagram -- 1G/2.5G/5G/10G/25G/50G MACsec
  • Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core
    • Encrypts using the AES Rijndael Block Cipher Algorithm.
    • Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST). FIPS-197 validated (AESAVS).
    • Processes 128-bit data blocks with 8, 16 or 32-bit data interface
    • Employs key sizes of 128 bits (AES128), 192, or 256 bits (AES256)
    Block Diagram -- Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core
  • 802.15.3 CCM AES Core
    • Small size: From 9,500 ASIC gates at 802.15.3 data Speeds.
    • High data rate: up to 8 Gbps for IEEE 802.15.3c / ECMA-387 (TC 48) / IEEE 802.11ad 60 GHz PHY
    • Completely self-contained: does not require external memory
    • Includes encryption, decryption, key expansion and data interface
    Block Diagram -- 802.15.3 CCM AES Core
  • ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
    • Support ONFi 4.0 IO Electrical Specification
    • Support Legacy up to 50MHz
    • Support NV-DDR2 with operating frequency up to 533Mbps
    • Support NV-DDR3 with operating frequency up to 800Mbps
    Block Diagram -- ONFi PHY 4.0 (FPHY+MDLL+SDLL Regulator) (Silicon Proven in TSMC 28HPC+)
  • TSMC CLN3FFP HBM4 PHY
    • IGAHBMZ03A is a High Bandwidth Memory 4 Physical  Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.
    • Fabricated in the TSMC 3 nm Advanced process node (N3P), it supports the data rate up to 12 Gbps per data pin in the DDR PHY Interface (DFI)-like 1:4 clock frequency ratio (HBM4 controller clock: WDQS = 1:4).
    Block Diagram -- TSMC CLN3FFP HBM4 PHY
  • JPEG encoder
    • Baseline JPEG compliant (ITU T.81), Motion JPEG
    • Up to 12 bits depth possible (default: 8 bit)
    • Super low latency (less than 1/10 of frame duration for rolling shutter cameras)
    • Lossy compression by default
    • Fully bit and cycle accurate co-simulation model available in Docker container
    Block Diagram -- JPEG encoder
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Semiconductor IP