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Compare 4,316 IP for TSMC from 112 vendors (1 - 10)
  • PCIe Gen2 PHY
    • PCI Express Gen 2 and Gen 1 compliant
    • Supports various PCI Express modes and extensions
    • Programmable amplitude and pre-emphasis
    • Programmable receiver equalization
    Block Diagram -- PCIe Gen2 PHY
  • PCIe Gen3 PHY
    • Low Risk - Silicon proven with Si characterization data
    • Excellent Interoperability
    • Superior Noise Immunity
    Block Diagram -- PCIe Gen3 PHY
  • PCI v2.1 Host Controller
    • The PCI Host controller offers a PCI 32-bit bus operating at 33MHz and supports PCI devices conforming to the PCI Local Bus Specification 2.1.
    • PCI Host Bridge contains an internal arbiter to manage up to 4 external devices 
    Block Diagram -- PCI v2.1 Host Controller
  • PCI v2.1 Master/Slave controller
    • The PCI master/slave controller is fully compliant with PCI Local Bus Specification, Revision 2.3.
    • It has a fully customizable PCI Configuration Space. The controller supports both 32- and 64-bit PCI bus paths.
    • The application interface can be configured as a 32-bit bit as well as a 64-bit interface as per requirements.
    Block Diagram -- PCI v2.1 Master/Slave controller
  • 3GPP Kasumi Accelerators
    • Wide bus interface (64-bit data, 128-bit keys) or 32-bit register interface.
    • Includes key scheduling hardware.
    • Modes Kasumi
    • Algorithms f8 and f9.
    • Fully synchronous design.
    • Low Speed, High Speed versions.
    Block Diagram -- 3GPP Kasumi Accelerators
  • 802.11i CCMP/TKIP IP Core
    • Implementation of the WLAN security standard (802.11i) requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and message authentication with the CCMP protocol and RC4/”Michael” cipher for the TKIP.
    • The WPA3 core is tuned for high data rate 802.11i applications (up to 2 Gbps for the CCMP protocol for 802.11n/802.11ac).
    Block Diagram -- 802.11i CCMP/TKIP IP Core
  • Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
    • One input word per clock without any backpressure
    • Design can switch stream, algorithm, mode, key and/or direction every clock cycle
    • GCM: throughput is solely determined by the data width, data alignment and clock frequency
    • XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available
    Block Diagram -- Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
  • RSA/ECC Public Key Accelerators with TRNG and AHB
    • Up to 4160-bit modulus size for RSA & 768-bit modulus for prime field ECC operations
    • Public key signature generation, verification and key negotiation with little involvement of host
    • NIST CAVP compliant for FIPS 140-3
    Block Diagram -- RSA/ECC Public Key Accelerators with TRNG and AHB
  • Small RSA/ECC Public Key Accelerators
    • The PKA-IP-28 is a family of Public Key Accelerator IP cores designed for full scalability and an optimal “performance over gate count” deployment.
    • Proven in silicon, the PKA-IP-28 public key accelerator addresses the unique needs of semiconductor OEMs and provides a reliable and cost-effective solution that is easy to integrate into SoC designs.
    Block Diagram -- Small RSA/ECC Public Key Accelerators
  • ChaCha20 Accelerators
    • The ChaCha-IP-13 (EIP-13) is an IP solution for accelerating the ChaCha20 cipher algorithm (RFC7539), supporting the NIST CTR mode up to 12.8 Gbps @ 300MHz.
    • Designed for fast integration, low gate count and full transforms, the ChaCha-IP-13 accelerator provides a reliable and cost-effective embedded IP solution that is easy to integrate into high-speed crypto pipelines.
    Block Diagram -- ChaCha20 Accelerators
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