IP for TSMC
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4,490
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for TSMC
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Ceva-Waves Bluetooth 5.4 Low Energy Baseband Controller / Link Layer, software and profiles
- Compliant with Bluetooth Low Energy specifications up to version 5.4
- Supports all mandatory and optional features of Bluetooth low energy
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TSMC CLN4P 4nm DDR5 PHY - 6400Mbps
- Supports DDR5
- DFI 5.1 compliant
- Supports x4, x8 and x16 DRAMs
- Up to 72 bits wide and up to 4 ranks
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LPDDR5X DDR Memory Controller
- JEDEC LPDDR5X/LPDDR5 devices compatible
- Data rates up to 8533Mbps
- Multiple ARM AMBA AXI4/AHB/APB & Custom interfaces
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Ultra-Low Phase Noise Digital LC PLL
- Wideband integrated jitter <400fs in integer mode, <800fs in fractional mode with high-speed / clean reference with active fractional noise cancellation
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MIPI C-PHY/D-PHY Combo RX+ IP 4.5Gsps/4.5Gbps in TSMC N5
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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ICE-IP-358 High-speed XTS-GCM Multi Stream Inline Cipher Engine, DPA resistant
- Silicon-proven implementation
- Fast and easy to integrate into SoCs
- Flexible layered design
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ICE-IP-338 High-speed XTS-GCM Multi Stream Inline Cipher Engine
- Performance and Configuration
- FIPS Certification
- Low Latency with Zero Variation
- Cryptographic Processing
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Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
- With Classifier, Look-Aside, 5-10 Gbps
- Silicon-proven implementation
- Fast and easy to integrate into SoCs
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250Mbps to 8.1Gbps Multi-protocol SerDes PMA, wire-bond
- Layout for wirebond packaging
- Very wide CDR range -- operates with data rates from 0.25Gbps to 8.1Gbps
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Ultra-low Jitter Fractional-N Frequency Synthesizer PLL (5nm - 180nm)
- Jitter-Power optimized to meet PCIe1-5 reference clock requirements - replaces 300mW/$2.50 clock chip
- Low area on chip -- keepouts = DRC limit in most cases