IP for TSMC

Compare 3,909 IP for TSMC from 106 vendors (1 - 10)

MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
- Technology is TSMC 22nm ULP 1p10M.
- Supply voltage can be applied 1.0V for core voltage, 1.8V for IO voltage.
- Maximum data rate of each channel is 1.5Gbps at High-speed mode for MIPI D-PHY Transmitter.
- Data rate of each channel is 609Mbps for FPD-Link(LVDS).
MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
- Renesas MIPI D-PHY Transmitter/Receiver can be used for analog Transmitter/Receiver of following interface.
- Technology is TSMC 40nm LP 1p6M (4x1z) .
- Supply voltage can be applied 1.1V for core voltage, 1.8V for IO voltage.
1.7GHz Multiplying PLL on TSMC 28nm
- Including Loop-filter
- VCO operating range : 850MHz - 1700 MHz
- Output frequency range : 850MHz -1700 MHz
- Input frequency range : 9.6MHz - 216MHz
5GHz Multiplying PLL on TSMC 28nm
- Including Loop-filter
- VCO operating range : 2500MHz - 5000 MHz
- Output frequency range : 1250MHz - 2500 MHz
- Input frequency range : 12MHz - 320 MHz
1.8GHz SSCG PLL on TSMC 28nm HPC+
- Including Loop-filter
- VCO operating range : 900MHz - 1800 MHz
- Output frequency range : 900MHz-1800 MHz
- Input frequency range : 12MHz - 192MHz
3.2GHz SSCG PLL on TSMC 12nm
- Including Loop filter
- VCO operating range : 1600MHz- 3200MHz
- Output frequency range: 400MHz- 3200MHz
- Input frequency range : 10MHz- 200MHz
4.3GHz SSCG PLL on TSMC 7nm
- Including Loop filter
- VCO operating range : 2000MHz-4300MHz
- Output frequency range: 500MHz-4300MHz
- Input frequency range : 10MHz- 200MHz
High Speed Single Port Compiler on TSMC 40nm ULP
- Low voltage
- Ultra low power data retention
- Self biasing
- Soft error immunity
32Gbps, 31 order, Pseudo Random Bit Sequence Generator / Checker
- This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps. Error count is accurate: no double counts or omissions regardless of error sequence or frequency of occurrence.
- Can be used as Generator, Checker or both. No inductors are used minimizing area and EM interference. Simple control interface, with low frequency asynchronous signals only.
32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator/Checker
- PRBS order: 7, 15 or 31 based on formulas: X1=X6^X7; X1=X14^X15; X1=X28^X31
- Full bit rate at input and output up to 32Gbps
- Generator, Checker and Counter functions
- Accurate error count: no omissions or double counts
- Full rate CMOS differential input data, centered with half-rate CMOS differential clock
- Full rate CMOS differential output data, aligned with half-rate CMOS differential clock

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