IP Catalog > Foundries > TSMC

IP for TSMC

Welcome to the ultimate IP for TSMC hub! Explore our vast directory of IP for TSMC
All offers in IP for TSMC
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (3,913)
Compare 3,913 IP for TSMC from 107 vendors (1 - 10)
  • Customizable Display Controller IP
    • CDC is a fully Customizable Display Controller IP supporting up to 16k resolutions (4096x4096 pixel) on a MIPI-DPI compliant parallel video output.
    • Several features can be configured at synthesis time and programmed at run time.
    • The display controller can be applied to e.g. FPGA systems with a resource optimized, application specific feature configuration or to ASIC projects applying a more generic feature set and thus more flexibility.
    Block Diagram -- Customizable Display Controller IP
  • Ultra-Low Latency 32Gbps SerDes IP in TSMC 12nm FFC
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Ultra-low latency 2/4/8-bit parallel interface mode for lowest possible latency
    Block Diagram -- Ultra-Low Latency 32Gbps SerDes IP in TSMC 12nm FFC
  • Ultra-Low Latency 32Gbps SerDes IP in TSMC 22nm ULP
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Ultra-low latency 2/4/8-bit parallel interface mode for lowest possible latency
    Block Diagram -- Ultra-Low Latency 32Gbps SerDes IP in TSMC 22nm ULP
  • 32Gbps SerDes IP in TSMC 12nm FFC
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Configurable low latency parallel data interface for optimal system performance
    Block Diagram -- 32Gbps SerDes IP in TSMC 12nm FFC
  • 32Gbps SerDes IP in TSMC 22nm ULP
    • Modular architecture supporting x1 to x16 lanes with a single CMU
    • Lane-based PLL architecture supporting flexible, independent data rates from 1.25 to 32Gbps
    • Configurable low latency parallel data interface for optimal system performance
    Block Diagram -- 32Gbps SerDes IP in TSMC 22nm ULP
  • MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
    • Technology is TSMC 22nm ULP 1p10M.
    • Supply voltage can be applied 1.0V for core voltage, 1.8V  for IO voltage.
    • Maximum data rate of each channel is 1.5Gbps at High-speed mode for MIPI D-PHY Transmitter.
    • Data rate of each channel is 609Mbps for FPD-Link(LVDS).
    Block Diagram -- MIPI D-PHY and FPD-Link (LVDS) Combinational Transmitter for TSMC 22nm ULP
  • MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
    • Renesas MIPI D-PHY Transmitter/Receiver can be used for analog Transmitter/Receiver of following interface.
    • Technology is TSMC 40nm LP 1p6M (4x1z) .
    • Supply voltage can be applied 1.1V for core voltage, 1.8V for IO voltage.
    Block Diagram -- MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
  • 1.7GHz Multiplying PLL on TSMC 28nm
    • Including Loop-filter
    • VCO operating range : 850MHz - 1700 MHz
    • Output frequency range : 850MHz -1700 MHz
    • Input frequency range : 9.6MHz - 216MHz
    Block Diagram -- 1.7GHz Multiplying PLL on TSMC 28nm
  • 5GHz Multiplying PLL on TSMC 28nm
    • Including Loop-filter
    • VCO operating range : 2500MHz - 5000 MHz
    • Output frequency range : 1250MHz - 2500 MHz
    • Input frequency range : 12MHz - 320 MHz
    Block Diagram -- 5GHz Multiplying PLL on TSMC 28nm
  • 1.8GHz SSCG PLL on TSMC 28nm HPC+
    • Including Loop-filter
    • VCO operating range : 900MHz - 1800 MHz
    • Output frequency range : 900MHz-1800 MHz
    • Input frequency range : 12MHz - 192MHz
    Block Diagram -- 1.8GHz SSCG PLL on TSMC 28nm HPC+
×
Semiconductor IP