IP for TSMC
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1.2V Thin Oxide GPIO on TSMC 28nm RF HPC+
- The 1.2V Thin Gate GPIO is an IP macro for on-chip integration. It is a 1.2V general purpose I/O that does not rely on thick-gate devices. Only thin-gate, 0.9V capable core MOS devices are used in the design.
- Supported features include core isolation, programmable slew rate compensation, programmable drive strength, input/output enable, pull select and pull enable. Extra features such as programmable hysteresis can be supported upon request.
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3.3V Capable GPIO on TSMC 28nm RF HPC+
- The 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.8V thick oxide MOS devices. It is controlled by 0.9V (core) signals.
- Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
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All Digital Fractional-N RF Frequency Synthesizer PLL in TSMC N6/N7
- Fractional Multiplication with frequencies up to 8GHz
- Extremely low jitter (sub 300fs RMS)
- Small size (< 0.05 sq mm)
- Low Power (< 7mW)
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All Digital Fractional-N PLL for Performance Computing in TSMC N6/N7
- Fractional multiplication with frequency up to 4GHz
- Low jitter (< 10ps RMS)
- Small size (< 0.01 sq mm)
- Low Power (< 5mW)
- Support for multi-PLL systems
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General Purpose All Digital Fractional-N PLL in TSMC N6/N7
- Low jitter (< 18ps RMS)
- Small size (< 0.01 sq mm)
- Low Power (< 3.5mW)
- Support for multi-PLL systems
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Low Power All Digital Fractional-N PLL in TSMC N6/N7
- Low power, suitable for IoT applications
- Good jitter, suitable for clocking digital logic.
- Extremely small die area (< 0.005 sq mm), using a ring oscillator
- Output frequency can be from 1 to 400 times the input reference, up to 1.5GHz
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TSMC CLN5FF GUCIe LP Die-to-Die PHY
- IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face advanced package.
- This GUCIe PHY not only supports UCIe specification rev 1.1 compliance physical layer and Raw D2D interface (RDI) but also optionally provides the
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MIPI I3C Target Device
- MIPI I3C Basic Specification v1.2 compiliance
- Native 32-bit CPU Interface
- Optional CPU interface wrappers (APB, AHB, AXI)
- Legacy I2C communication with 7-bit Static Address
- I3C Single Data Rate (SDR) mode
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USB Full Speed Transceiver
- Exceeds USB 2.0 Full Speed specification.
- Trimmed pull up resistor.
- Enable / suspend feature.
- DPF and UFP options available.
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PCIe 6.0 PHY, TSMC N3A x4 1.2V, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
- Supports the latest features of PCIe 6.x and CXL 3.x specifications
- Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
- Delivers more power efficiency across channels with unique DSP algorithms
- Enables near zero link downtime with patent-pending diagnostic features