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USB IP

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Search (732)
Compare 732 USB IP from 50 vendors (1 - 10)
  • USB4 v2.0 Verification IP
    • Fully compliant with USB4 specification v2.0 (October 2022) and Connection Manager version 2.0.
    • Supports USB3.2 Specification, Revision 1.1 and backward compatibility to USB2.0.
    • Supports USB Power Delivery Release 3.1, Version 1.8 and Type-C v2.2.
    • Supports Thunderbolt (TBT3) interoperability.
    Block Diagram -- USB4 v2.0 Verification IP
  • USB Type-C and Power Delivery Verification IP
    • Compliant with standard USB PD Rev 3.1 V1.8, Type-C Rev2.2 & USB type C Port controller interface Rev2.0 V1.3.
    • Supports enabling USB4 (Gen 2/Gen 3/Gen 4) over type C Connectors.
    • Supports both Standard Power range (SPR) and Extended Power range (EPR) modes of operation.
    • Supports all Fixed voltage supply, Programmable power supply (PPS) and Adjustable Votlage supply (AVS).
    Block Diagram -- USB Type-C and Power Delivery Verification IP
  • USB 4.0 Verification IP
    • Fully compliant with USB4 specification v1.0 (March 2022) and Connection Manager version 1.0.
    • Supports USB3.2 Specification, Revision 1.1 and backward compatibility to USB2.0.
    • Supports USB Power Delivery Release 3.1, Version 1.8 and Type-C v2.2.
    • Supports Thunderbolt (TBT3) interoperability.
    Block Diagram -- USB 4.0 Verification IP
  • USB 4.0 Retimer Verification IP
    • Fully compliant with USB4 specification v1.0 (March 2022), Connection Manager version 1.0 and USB4 Re-Timer Specification Rev 1.0.
    • Supports USB3.2 Specification, Revision 1.1 and backward compatibility to USB2.0.
    • Supports USB Power Delivery Release 3.1, Version 1.8 and Type-C v2.2.
    • Supports Thunderbolt (TBT3) interoperability.
    Block Diagram -- USB 4.0 Retimer Verification IP
  • USB 4.0 HUB Verification IP
    • Fully compliant with USB4 specification v1.0 (March 2022) and Connection Manager version 1.0
    • Supports USB3.2 Specification, Revision 1.1 and backward compatibility to USB2.0.
    • Supports USB Power Delivery Release 3.1, Version 1.8 and Type-C v2.2.
    • Supports Thunderbolt (TBT3) interoperability.
    Block Diagram -- USB 4.0 HUB Verification IP
  • USB 3.2 Verification IP
    • Fully compliant with USB 3.2 specification version 1.1, xHCI Specification Revision 1.2, and Pipe Interface 6.1.1 with Message Bus Interface for USB3.2 Architecture with backward compatibility to USB3.1, USB3.0 and USB2.0 (including USB2.0, USB 3.0. OTG)
    • Supports USB Type-C.
    • Supports up to 128 devices including hub and device on any tier level.
    • Supports 15 IN and 15 OUT and 1 control endpoint for each device.
    Block Diagram -- USB 3.2 Verification IP
  • USB 2.0 Verification IP
    • Supports BOT Protocol and UASP Bulk transfers also.
    • Supports Multi RootHUB ports to connect multiple USB2 HUBs/Devices with USB2 HOST
    • Fully compliant to the USB2.0, xHCI 1.1, Utmi+ 1.0 & ULPI Transceiver Interface Specification with backward compatility to USB 1.1.
    • Supporting On-The-Go which is fully compliant OTG Rev 2.0, V1.1a.
    Block Diagram -- USB 2.0 Verification IP
  • eUSB2 v2 Verification IP
    • Supports eUSB2-v2 extended Symmetric data rates (HSSx), extended Asymmetric data rates (HSUx & HSDx)
    • Supports Scrambling and Bit Stuffing
    • Supports the Disconnect/Connect with Analog Ping in Extended High-Speed Signaling at nave mode.
    • Supports Protocol Extended Token transactions for LPM Ack handshake.
    Block Diagram -- eUSB2 v2 Verification IP
  • eUSB2 v1 Verification IP
    • Supports eUSB2-v1 Low-Speed,Full-Speed and High-Speed Bus State Representaons.
    • Supports all encoding of eUSB2-v1 Control Message (CM) Signaling for nave and repeater mode configurations.
    • Supports the Disconnect/Connect with Digital Ping in Full/Low speed & Analog Ping with High-Speed Signaling at nave and repeater modes.
    • Supports Protocol Extended Token transactions for LPM Ack handshake.
    Block Diagram -- eUSB2 v1 Verification IP
  • USB 3.2 ReTimer
    • USB 3.2 Retimer softcore is designed for use in USB Port/Cable Retimer applications with USB SuperSpeed Plus/SuperSpeed link operations.
    • The IP has been verified in simulation and is synthesis clean for FPGA implementations
    Block Diagram -- USB 3.2 ReTimer
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