USB IP

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Compare 692 USB IP from 45 vendors (1 - 10)
  • USB PHY Solution
    • Brite provides USB2.0 OTG PHY which is a complete mixed-signal IP solution designed to implement OTG connectivity for a System-on-Chip (SoC) design.
    • The USB2.0 OTG PHY supports the USB2.0 480Mbps protocol and data rate, and is backward compatible with the USB 1.1 1.5Mbps and 12Mbps protocol and data rates.
    • It has been verified by a number of end products, especially suitable for the current popular internet of things applications.
    Block Diagram -- USB PHY Solution
  • USB 20Gbps Device Controller
    • Leveraging the benefits of USB 10Gbps and 5Gbps device controller, USB 20Gbps is designed using the FPGA built-in transceiver.
    • It is a one-stop solution for all USB requirements ranging from USB 3.2 to USB 2.0.
    • It supports SuperSpeed+ (SSP x2/x1), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes.
    Block Diagram -- USB 20Gbps Device Controller
  • USB 2.0 On-The-Go (USB20OTG)
    • The USB 2.0 On-The-Go (OTG) IP Core is a 32-bit Avalon interface compliant core and supports ULPI interface.
    • It supports both USB Host and USB Device peripheral functionality.
    • While acting as USB Host, it supports High Speed (HS), Full Speed (FS) and Low Speed (LS) modes.
    • While acting as USB Device peripheral, it supports High Speed (HS) and Full Speed (FS) modes.
    Block Diagram -- USB 2.0 On-The-Go (USB20OTG)
  • USB 10Gbps Device Controller
    • Leveraging the benefits of USB 3.2 Gen 1 device controller, USB 3.2 Gen 2 is designed using the FPGA built-in transceiver.
    • It is a one-stop solution for all USB requirements ranging from USB 3.2 to USB 2.0.
    • It supports SuperSpeed+ (SSP), SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes.
    Block Diagram -- USB 10Gbps Device Controller
  • USB 2.0 HUB (USB20HUB)
    • The USB 2.0 Hub IP core provides a link between the USB2.0 Host and multiple USB peripherals via UTMI + Low pin interface (ULPI).
    • It supports High speed, Full speed and Low speed peripheral devices.
    • Its rich features and ease of use makes it more suitable for embedded applications.
    Block Diagram -- USB 2.0 HUB (USB20HUB)
  • USB 2.0 Device with FIFO Interface (USB20HF)
    • USB 2.0 device, FIFO interface (USB20HF) IP Core provides FIFO interface for endpoints and ULPI interface for Host communication.
    • It supports 15 IN and OUT endpoints as per the USB standards which are configurable in Bulk, Interrupt and Isochronous modes as per the requirement.
    • The core supports High Speed (480 Mbps), Full Speed (12 Mbps) and Low Speed (1.5 Mbps) functionality. It comes with three pre-configured endpoints - Control, Bulk IN, and Bulk OUT.
    Block Diagram -- USB 2.0 Device with FIFO Interface (USB20HF)
  • USB 2.0 Device, Software based enumeration RAM Interface (USB20SR)
    • The USB 2.0 Device, Software Enumeration (USB20SR) IP Core is a RAM based USB 2.0 device core with 32-bit Avalon/AXI/AHB Lite interface and ULPI interface support.
    • The core supports High Speed(480 Mbps) , Full Speed(12 Mbps) and Low Speed(1.5 Mbps) functionality.
    Block Diagram -- USB 2.0 Device, Software based enumeration RAM Interface (USB20SR)
  • USB 2.0 Device, Software Enumeration FIFO Interface (USB20SF)
    • The USB 2.0 Device, Software Enumeration FIFO interface (USB20SF) IP Core is a FIFO based USB 2.0 device core with 32-bit Avalon/AXI/AHB Lite interface and ULPI interface support.
    • Avalon/AXI/AHB Lite interface allows to manage the control transfer using software, provides flexibility, while FIFO interface allows to transfer the data over non-control endpoint ensuring highest throughput.
    Block Diagram -- USB 2.0 Device, Software Enumeration FIFO Interface (USB20SF)
  • USB 2.0 Host Controller
    • Supports Low Speed (1.5 Mbps), Full Speed (12 Mbps) and High Speed (480 Mbps)
    • Supports UTMI+Low Pin Interface (ULPI)
    • Supports ULPI PHY low power mode and register access through software
    • Supports 15 Bulk and 2 Interrupt Endpoints
    Block Diagram -- USB 2.0 Host Controller
  • USB 1.1 Device, Software Based Enumeration (USB11SR)
    • The USB 1.1 Device, Software Based Enumeration IP Core is RAM based USB 1.1 device core with 32-bit Avalon interface.
    • The core supports Full Speed (12 Mbps) functionality and Low Speed (1.5 Mbps) functionality can be added as per customer request with additional charges.
    • The core supports three preconfigured Control, Bulk IN and Bulk OUT endpoints.
    • It can be configurable for up to 15 IN/OUT endpoints on customer request on chargeable basis.
    Block Diagram -- USB 1.1 Device, Software Based Enumeration (USB11SR)
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