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IoT Processor IP Cores

Welcome to the ultimate IoT Processor IP hub! Explore our vast directory of IoT Processor IP Cores.

The IoT Processor IP Cores are ideal for M2M protocol stack and baseband PHY control, including LTE Cat-NB1, Cat-M1, Sigfox, LoRa, Wi-Fi 802.11n, 802.11ah, Bluetooth, Bluetooth Low Energy, and Zigbee/Thread. They also support positioning and motion-sensing functions, including GNSS (GPS, Beidou, GLONASS, Galileo), fusion of multiple indoor positioning and activity sensors, voice activation, and sound processing.

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Compare 16 IoT Processor IP Cores from 9 vendors (1 - 10)
  • IP cores for ultra-low power AI-enabled devices
    • Ultra-fast Response Time
    • Zero-latency Switching
    • Low Power
    Block Diagram -- IP cores for ultra-low power AI-enabled devices
  • High Performance Scalable Sensor Hub DSP Architecture
    • Self contained, specialized sensor hub on-device processor
    • Unifies multi-sensor processing with AI and sensor fusion
    • Highy-configurable 8-way VLIW architecture
    Block Diagram -- High Performance Scalable Sensor Hub DSP Architecture
  • Powerful vector DSP for 5G-Advanced Massive Compute
    • Designed to meet the demanding requirements of modern 5G and 5G-Advanced networks
    Block Diagram -- Powerful vector DSP for 5G-Advanced Massive Compute
  • Single channel ADAS chip with FuSa monitor
    • The SFA 250A has been designed to be easy to adapt to suit the support needs of the customer’s IP as it is scalable, both in terms of function and performance, as well as modular as multiple versions can be combined to form larger solutions.
    Block Diagram -- Single channel ADAS chip with FuSa monitor
  • High Throughput Rate OFDM Baseband PHY Processor
    • Custom OFDMA system based on 802.16e standard features.
    • Complete Back-end User IF for primitive MAC integration.
    Block Diagram -- High Throughput Rate OFDM Baseband PHY Processor
  • ARC IoT Communications IP Subsystem
    • Integrated, pre-verified hardware and software IP subsystem
    • ARC EM11D processor with DSP extensions delivers extremely low gate count and highly efficient processing performance
    • Hardware accelerators for key communications functions such as Viterbi decoding dramatically reduce cycle counts and energy consumption
    • Integrated peripherals provide a wide range of SoC connectivity options for SoC/MCUs
    Block Diagram -- ARC IoT Communications IP Subsystem
  • Data Fusion IP Subsystem
    • Integrated, pre-verified hardware and software IP subsystem
    • ARC EM processors with cache and DSP extensions deliver extremely low gate count and highly efficient processing performance
    • Extensive library of software DSP functions enable sensor signal processing
    • Hardware accelerators boost performance efficiency and reduce power consumption
    Block Diagram -- Data Fusion IP Subsystem
  • ARC Data Fusion Voice/Speech Option
    • Integrated, pre-verified hardware and software IP subsystem
    • ARC EM processors with cache and DSP extensions deliver extremely low gate count and highly efficient processing performance
    • Extensive library of software DSP functions enable sensor signal processing
    • Hardware accelerators boost performance efficiency and reduce power consumption
    Block Diagram -- ARC Data Fusion Voice/Speech Option
  • U54 Linux-capable RISC V application processor
    • Fully compliant with the RISC-V ISA specification
    • RV64GC U54 Application Core
    • Integrated 128KB L2 Cache with ECC
    • Real-time capabilities
    Block Diagram -- U54 Linux-capable RISC V application processor
  • E24 High-performance microcontroller with hardware support
    • RISC-V ISA - RV32IMAFC
    • Machine and User Mode with 4 Region Physical Memory Protection
    • 3-stage pipeline with Simultaneous Instruction and Data Access
    • 2 Banks of Tightly Integrated Memory
    Block Diagram -- E24 High-performance microcontroller with hardware support
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