Timer/Watchdog IP

The M429GEN IP implements a synchronous single-chip ARINC 429 Transmit and Receive Controller capable of linking one CPU to one or several ARINC 429 bus.
The IP controls all ARINC 429 bus specific sequences, protocol and timing. The M429GEN IP interface allows the parallel-bus microprocessor to communicate bidirectionally with the ARINC 429 bus.

The BRIDGE_UART_I2C IP Core provides a simple and convenient way to interface a standard UART bus to a standard I2C bus.
The circuit operates as a completely transparent ‘bridge’ between the two buses and allows I2C peripherals to be programmed using a set of basic commands over a (UART) serial interface.

The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.

UART eVC is a fully documented, off the shelf component for Cadence Specman Elite functional verification environment. At the heart of every asynchronous serial system is the Universal Asynchronous Receiver/Transmitter (UART).
The UART is responsible for implementing the asynchronous communication process as both a transmitter and a receiver (both encoding and decoding data frames). The UART not only controls the transfer of data, but the speed at which communication takes place.

The serial digital interface (SDI) II Intel FPGA intellectual property (IP) core implements a transmitter, receiver or full-duplex SDI at standard definition, high definition or 3G to 12G rate as defined by the Society of Motion Picture and Television Engineers
The SDI II IP core supports multiple standards
These modes provide automatic receiver rate detection and transceiver dynamic reconfiguration.

The Universal Asynchronous Receiver/Transmitter (UART) is a hardware device that translates data between parallel and serial forms.
UARTs are commonly used in conjunction with communication standards such as TIA (formerly EIA) RS-232, RS-422 or RS-485.

The APB Timer module is a sixteen-bit down counter with a selectable prescaler. Prescale values of 1, 16 and 256 can be selected.
The prescaler extends the timer’s range at the expense of precision.
The Timer provides two modes of operation that provide a free running value and also periodic interrupts.

This is a complete implementation of a 16550 UART.
The UART contains the following main sections: Configuration Registers, Baud Rate, Generator, Transmitter, Receiver, Interrupt Generation Logic, Modem Control Logic

The Watchdog Timer is useful in monitoring the condition where a CPU and software get into an unrecoverable unknown or “stuck” state.
Software periodically “kicks” the watchdog by writing to it to reset its timeout counters.
The Watchdog Timer module is a programmable reset controller module.

The UART Verification IP provides a comprehensive solution for validating UART communication interfaces in System-on-Chip (SoC) designs. It simulates both transmission and reception functionality to ensure data integrity. This IP supports error injection, debugging tools, and protocol compliance checking. It is ideal for ensuring reliability and protocol compliance in UART-based peripherals used in various applications, from simple devices to advanced systems.