IP for GLOBALFOUNDRIES

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Compare 1,047 IP for GLOBALFOUNDRIES from 58 vendors (1 - 10)
  • UHF RFID tag IP with 3.6kBit EEPROM and -18dBm sensitivity
    • 130GF_RFID_EPCGen2_01 IP is intended for use in passive UHF transponder applications.
    • IP derives its operating power from an RF electromagnetic field generated by a reader, which is received and rectified by the IP.
    • The tag IP sends the answer back to the reader using a backscatter modulation technique.
    Block Diagram -- UHF RFID tag IP with 3.6kBit EEPROM and -18dBm sensitivity
  • 12-bit 40nm 1.1V 64MHz-to-340MHz continuous-time Delta-Sigma ADC
    • Integrated Dual-Channel Continuous-time Delta-Sigma Modulator (I + Q)
    • Integrated Dual decimate-by-8 Cascaded-Integrator-Comb Decimation Filter
    Block Diagram -- 12-bit 40nm 1.1V 64MHz-to-340MHz continuous-time Delta-Sigma ADC
  • Crystal Oscillators
    • The crystal oscillator macros are available in a wide range of industry-standard quartz crystals and MEMS resonators operating in the fundamental mode in the 32 kHz to 80 MHz range.
    • These oscillators, which are both power and area efficient, have a programmable transconductance to allow users to find the optimal balance between jitter and power consumption.
    Block Diagram -- Crystal Oscillators
  • Free running oscillators
    • Compact and low power
    • No external components
    • Baseline CMOS logic process masks only
    • Excellent frequency precision over PVT after trimming
    Block Diagram -- Free running oscillators
  • LVDS Deserializer IP
    • The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
    • Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components.
    Block Diagram -- LVDS Deserializer IP
  • LVDS Serializer IP
    • The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels.
    • The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components.
    Block Diagram -- LVDS Serializer IP
  • 4.25 Gbps Multi-Standard SerDes
    • The MXL4254A is a silicon proven Quad Gigabit SerDes implemented in digital CMOS technology. Each of the four channels supports data rate up to 4.25 Gbps.It is compatible with router-backplane links, PCI Express, SATA, RapidIO, 10 Gbps Ethernet (XAUI), FibreChannel, SFI-5, SPI-5, and other communication applications.
    Block Diagram -- 4.25 Gbps Multi-Standard SerDes
  • 11 Bit 100 kS/s Ultra-Low Power SAR ADC on GlobalFoundries 22FDSOI
    • The ADC IP is a general-purpose successive approximation converter for low-power medium resolution applications. Sample rate, resolution and power consumption are configurable.
    • It is built using typical differential capacitor-DAC architecture, clocked comparator and bootstrapped switches. No additional reference voltage is required, achieving lmost rail-to-rail input. The target applications are environmental and biomedical signal processing.
    Block Diagram -- 11 Bit 100 kS/s Ultra-Low Power SAR ADC on GlobalFoundries 22FDSOI
  • ULP Clock-Generator - GLOBALFOUNDRIES 22FDX
    • ABB-enabled, All-Digital PLL clock generator for ultra-low power clocking in highly energy efficient Systems on Chip
    • The Ultra-Low Voltage Clock Generator is targeted at Systems on Chip (SoCs) employing advanced power management techniques.
    • The robust, fully digital architecture allows operation in a wide voltage and frequency range. Unique fast lock and instant frequency change features maximize the energy efficiency of the targeted systems.
    Block Diagram -- ULP Clock-Generator - GLOBALFOUNDRIES 22FDX
  • Body bias voltage generator - GLOBALFOUNDRIES 22FDX
    • The ABX Generator IP is a body bias voltage generator for the ABX Platform for GLOBALFOUNDRIES 22FDX® technology.
    • It contains a closed loop body bias regulation loop to generate N-well and P-well bias voltages for adaptive compensation of process, voltage and temperature (PVT) variations during device operation.
    Block Diagram -- Body bias voltage generator  - GLOBALFOUNDRIES 22FDX
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