IP for GLOBALFOUNDRIES

Compare 1,189 IP for GLOBALFOUNDRIES from 63 vendors (1 - 10)

USB 3.1 Cable Marker IP
- USB PD 3.1 compliant.
- Single chip solution – just two external capacitors.
- 4 pin package.
- Less than 1mm2 area in 180nm.
- PROM programmed through vendor message protocol.
- Based on Obsidian’s mature PD technology.
- Integrated PROM enables customized response to a wide range of vendor requirements.
- Active Ra pulls down only requires 10uA at 5V., but is <1K below 2V.
- Power <5mW. Enabled by CC data activity. I.e. very low duty cycle.
- Programming can be done after assembly into the cable. Fuse lock function.
- Supports low cost, 4 layer PCB assembly.
LPDDR5T / LPDDR5X / LPDDR5 Controller
- Support for all LPDDR5T/5X/5 devices
- Bank management logic monitors status of each bank
- Queue-based user interface with reordering scheduler
- Look-ahead activate, precharge, and auto-precharge logic
- Parity protection for all stored control registers
- PHY interface based on DFI 5.1 standard
Multiprotocol SerDes PMA
- Supports over 30 protocols including CEI 6G & 11G SR, MR, LR, Ethernet 10GBASE-X/S/K/R, PCIe Gen1/2/3/4, V-by-One HS/US, CPRI, PON, OTN/OTU, 3GSDI, JESD204A/B/C, SATA1-3, XAUI, SGMII
- Programmable (De)Serialization width: 8, 10, 16, 20, 32, or 40 bit
- Tx ring PLL includes fractional multiplication, spread spectrum and Jitter Cleaner function for Sync-E and OTU
- Core-voltage line driver with programmable pre-and post-emphasis
eFPGA IP - 100% third party standard cells
- Every element of the eFPGA can be defined in numbers: logic cells, adaptive DSP (with and without FIR engine, add & mult size, amount), RAM (type and amount) and IOs.
- In addition, Menta eFPGA IP Cores being 100% standard cells based, multiple power / performances trade-off can be achieved based on customer requirements.
- The eFPGA IP Cores are provided as hard IPs (GDSII).
- Menta eFPGA IP Cores use standard cells, and as such integrate smoothly into any standard ASIC design flow. Designers use RTL as the input to our software Origami Programmer to generate the eFPGA program file (bitstream) and obtain accurate performance evaluation.
Complete USB Type-C Power Delivery IP
- Mixed signal Analog Front End Macros for 65n, 130n, 150nm, and 180n technologies.
- RTL code from AFE to I2C compatible register set.
- Stand alone C code for Protocol, Device Policy Manager, and System Policy Manager.
- IP demonstration & development board, with compliance reports.
- Full chip integration of USB Type-C, and associated software.
TESIC RISC-V CC EAL5+ Secure Element Soft/Hard Macro
- CC EAL5+ secure microcontroller system
- CC EAL5+ secure cryptography
- CC EAL5+ security sensors
TESIC CC EAL5+ Secure Element IP Core
- CC EAL5+ secure microcontroller system
- CC EAL5+ secure cryptography
- CC EAL5+ security sensors
Ultra low-power 2.4 GHz transceiver for Bluetooth Low Energy 5
- Voltage supply: 1.3V down to 1V, with graceful degradation down to 0.9V
- Compliant with direct operation from 1.2V battery
24-bit Cap-less ADC 104.5 dB SNR low power and low latency 4 channels
- I2C and APB control interface
- Embedded low noise voltage regulator for best resilience to power supply noise
Ultra-low power 32 kHz RC oscillator designed in GlobalFoundries 22FDX
- Ultra-low power for best-in-class power consumption of the always-on domain during sleep / deep sleep modes
- Fast wake-up
- Active, shutdown and stand-by mode