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General Purpose Processor IP

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Search (445)
Compare 445 General Purpose Processor IP from 68 vendors (1 - 10)
  • 64-bit in-order RISC-V Customisable IP Core
    • Ready for the most demanding workloads, Avispado supports large memory capacities with its 64-bit native data path. With its complete MMU support, Avispado is also Linux-ready, including multiprocessing.
    Block Diagram -- 64-bit in-order RISC-V Customisable IP Core
  • 64-bit Out-of-Order RISC-V Customisable IP Core
    • Ready for the most demanding workloads, Atrevido supports large memory capacities with its 64-bit native data path. With its complete MMU support, Atrevido is also Linux-ready, including multiprocessing.
    Block Diagram -- 64-bit Out-of-Order RISC-V Customisable IP Core
  • High performance, low power, 8-bit processor
    • The M8051EW and M8051W microcontroller cores are high performance versions of the popular 8051 8-bit microcontroller.
    • The M8051EW includes an On-Chip Instrumentation (OCI) debug unit supporting advanced debug operations (start/stop/single step, breakpoints, and trace) through an IEEE 1149.1 (JTAG) interface.
    • The M8051W does not include the OCI debug unit and, instead, provides limited debug capabilities (start/stop/single step) through a native debug interface.
    Block Diagram -- High performance, low power, 8-bit processor
  • ColdFire V4 Core & Standard Product Platform (SPP) C2
    • The ColdFire V4 Core & Standard Product Platform (SPP) C2 (CFV4SPPC2) combines the ColdFire V4 Core with industry proven platform peripherals to form a complete high performance micro-controller subsystem supported by a vast ecosystem of development tools and runtime software.
    Block Diagram -- ColdFire V4 Core & Standard Product Platform (SPP) C2
  • ColdFire V4 Core with industry proven platform peripherals
    • The ColdFire V4 Core & Standard Product Platform (SPP) C1 (CFV4SPPC1) combines the ColdFire V4 Core with industry proven platform peripherals to form a complete high performance micro-controller subsystem supported by a vast ecosystem of development tools and runtime software.
    Block Diagram -- ColdFire V4 Core with industry proven platform peripherals
  • ColdFire V4 Core & Standard Product Platform
    • The ColdFire V4 Core & Standard Product Platform (CFV4SPP) combines the ColdFire V4 Core with industry-proven platform peripherals to form a complete high-performance micro-controller subsystem supported by a vast ecosystem of development tools and runtime software.
    Block Diagram -- ColdFire V4 Core & Standard Product Platform
  • ColdFire V4 Processor delivering 500 DMIPS of performance
    • The ColdFire V2 Core & Standard Product Platform (CFV2SPPC1) combines the ColdFire V2 Core with industry-proven platform peripherals to form a complete low-cost, low-power microcontroller subsystem supported by a vast ecosystem of development tools and runtime software.
    • The CFV2SPPC1 is the same ColdFire V2 processor core and platform/peripheral IP implemented in NXP MCF5208 devices.
    Block Diagram -- ColdFire V4 Processor delivering 500 DMIPS of performance
  • ColdFire V2 Core with single Fast Ethernet and AMBA peripherals connected in a subsytem
    • Multi-AHB crossbar switch (AXBS) connects multiple masters with various slave IP blocks
    • External Bus Interface for glueless connection to external memory devices
    • 10/100 Fast Ethernet Controller (FEC) with direct memory access (DMA)
    • Queued serial peripheral interface (QSPI)
    Block Diagram -- ColdFire V2 Core with single Fast Ethernet and AMBA peripherals connected in a subsytem
  • ColdFire V2 Core with AMBA peripherals connected in a subsytem
    • Building upon the 68K foundation, ColdFire offers RISC performance with industry-leading code density and a rich set of connectivity peripherals.
    • By supporting variable-length instructions (16-, 32- or 48-bits long), the ColdFire Architecture enables higher code density than traditional 32- and 64-bit RISC machines.
    • More efficient use of on-chip memory reduces bus bandwidth and external memory requirements, resulting in lower system cost.
    Block Diagram -- ColdFire V2 Core with AMBA peripherals connected in a subsytem
  • ColdFire V2 IP Core low-gate count, high performance ColdFire architecture
    • Variable-length RISC, clock-multiplied core
    • 166-MHz in typical 130-nm process
    • Independent, decoupled pipelines: 2-stage instruction fetch pipeline (IFP); 2-stage operand execution pipeline (OEP); FIFO instruction buffer is the decoupling mechanism
    • 16 user-accessible, 32-bit general purpose registers (GPRs)
    Block Diagram -- ColdFire V2 IP Core low-gate count, high performance ColdFire architecture
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