General Purpose Processor IP
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Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex
- Gen#2 of 64-bit RISC-V core with out-of-order pipeline based complex. Designed for a range of applications requiring maximum single thread performance in Linux-capable devices. Improved performance compared with Gen#1.
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64-bit RISC-V core with in-order single issue pipeline. Tiny Linux-capable processor for IoT applications.
- 64-bit RISC-V core with in-order single issue pipeline based complex.
- Tiny Linux-capable processor optimized for low power and small area.
- Ideally fits IoT applications requiring Linux.
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Vector-Capable Embedded RISC-V Processor
- The EMSA5-GP is a highly-featured 32-bit RISC-V embedded processor IP core optimized for processing-demanding applications.
- It is equipped with floating-point and vector-processing units, cache memories, and is suitable for concurrent execution in a multi-processor environment.
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Compact Embedded RISC-V Processor
- The BA5x-CM is a feature-rich 32-bit deeply embedded processor.
- Equipped with a floating-point unit and an instruction cache memory and supporting concurrent execution in a multiprocessor environment, it is well-suited to a wide range of edge IoT and similar applications.
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Tiny, Ultra-Low-Power Embedded RISC-V Processor
- The BA5x-TN is a compact, ultra-low power, 32-bit, deeply embedded processor IP core.
- With a two-stage execution pipeline, the processor implements the Embedded variant of the base RV32 ISA (RV32E).
- It uses just 16 general-purpose compressed instructions and omits other resource-demanding extensions.
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Enhanced-Processing Embedded RISC-V Processor
- The BA5x-EP is a highly-featured 32-bit RISC-V embedded processor IP core optimized for complex, processing-demanding applications.
- It is equipped with a floating-point unit and cache memories, supports hardware-level virtualization, and is suitable for concurrent execution in a multi-processor environment.
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Low-Power Embedded RISC-V Processor
- The BA5x-LP is a highly efficient, low-power, 32-bit, deeply embedded processor IP core.
- The two-stage pipeline processor implements either the RV32I or RV32E instruction set.
- It comes pre-configured with the Multiply/Divide (M) and Compressed Instruction (C) extensions, providing a more flexible and capable platform without a significant increase in area or power.
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Data Movement Engine - Efficient data-processing and simultaneous multi-threading, low latency and deterministic data access
- Efficient throughput with the first RISC-V core to support up to 4-way multithreading
- Highly scalable multi-core, multi-cluster coherent computing solution
- MIPS Enhancements for increased connectivity and throughput
- Use in 5G/6G Comms Infrastructure, Automotive Gateways, Embedded & Datacenter
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8-stage dual issue, in-order, superscalar processor with dual vector processing units (1024-bit VLEN/512-bit DLEN)
- New RVA23 support
- New RVV1.0 512-bit vector engine
- New SSCI interface added alongside VCIX
- New instructions and extensions
- New improved memory subsystem
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Highly customizable processor IP supporting the Lua scripting language
- Native execution of the Lua scripting language
- Build-time configurable
- Run-time configurable
- Each processor core is heterogeneous
