IP for Samsung

The HBM3 IP consists of a PHY and memory controller optimized for Samsung SF4X process to support the HBM3 memory standard (JESD238A) operating at up to 9.6 Gbps/pin.
The HBM3 IP is designed for high memory throughput and low latency applications while minimizing area and power consumption.

A Samsung 11nm Flip-Chip I/O library with dynamically switchable 1.8V/3.3V GPIO with fail-safe capability, 5V I2C / SMBus open-drain cell, 5V OTP cell, 1.8V 3.3V analog cells, and associated ESD.
A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
The GPIO cell can be configured as input, output, open source, or open drain with an optional internal 50K ohm pull up or pull down resistor.

These eFPGA IP cores offer designers the flexibility to tailor resources to their application requirements, available as either Soft RTL or Hard GDSII IP.
Our standard-cell-based approach facilitates rapid porting to new process geometries or variants, including industrial and rad-hard grade versions.

The agilePMU Subsystem is an efficient and highly integrated Power Management Unit for SoCs/ASICs.
Featuring a Power-On-Reset (POR), multiple Low Drop-Out (LDO) regulators, and an associated reference generator.
The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities.

The agileSensorIF Subsystem is an efficient and highly integrated sensor interface for SoCs/ASICs.
Featuring multiple Analog-to-Digital Converters (agileADC), Digital-to-Analog Converters (agileDAC), low-power programmable analog comparators (agileCMP_LP), and an associated reference generator (agileREF).
The agileSensorIF Subsystem enables easy interaction with the analog world.