IP for Samsung

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Compare 249 IP for Samsung from 28 vendors (1 - 10)
  • Multi-Standard-Serdes (MSS) IP optimized for Medium Reach (MR) and Very Short Reach (VSR) applications
    • The ApolloCORE(MR/VSR) Multi-Standard-Serdes (MSS) IP is optimized for Medium Reach (MR) and Very Short Reach (VSR) applications.
    • It is a highly configurable IP that supports all leading edge NRZ and PAM data center standards from 1Gbps to 112Gbps.
    Block Diagram -- Multi-Standard-Serdes (MSS) IP optimized for Medium Reach (MR) and Very Short Reach (VSR) applications
  • UCIe Die-to-Die PHY
    • High Bandwidth Density and Data Rates
    • Package Configurability
    • Energy Efficiency
    • Fully Integrated Solution
    Block Diagram -- UCIe Die-to-Die PHY
  • High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X
    • The HBM3 IP consists of a PHY and memory controller optimized for Samsung SF4X process to support the HBM3 memory standard (JESD238A) operating at up to 9.6 Gbps/pin.
    • The HBM3 IP is designed for high memory throughput and low latency applications while minimizing area and power consumption.
    Block Diagram -- High Bandwidth Memory 3 (HBM3/3E) IP optimized for Samsung SF4X
  • 1.8V/3.3V Switchable GPIO with 5V I2C Open Drain and Analog Cells in Samsung 11nm
    • A Samsung 11nm Flip-Chip I/O library with dynamically switchable 1.8V/3.3V GPIO with fail-safe capability, 5V I2C / SMBus open-drain cell, 5V OTP cell, 1.8V 3.3V analog cells, and associated ESD.
    • A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
    • The GPIO cell can be configured as input, output, open source, or open drain with an optional internal 50K ohm pull up or pull down resistor.
    Block Diagram -- 1.8V/3.3V Switchable GPIO with 5V I2C Open Drain and Analog Cells in Samsung 11nm
  • LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
    • Compliant for JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
    • DFI 5.1 specification PHY Interface Compliant
    • Support up to 4 ranks
    • x16 and x32 channel support
    Block Diagram -- LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
  • LPDDR5/4x/4 PHY IP for Samsung 14LPU
    • Compliant with JEDEC standards for LPDDR5/4x/4 with PHY standards
    • DFI 5.0 Interface Compliant
    • Supports 1,2, or 4 ranks
    • Multiple frequency states
    Block Diagram -- LPDDR5/4x/4 PHY IP for Samsung 14LPU
  • LPDDR5T / LPDDR5X / LPDDR5 Controller
    • Support for all LPDDR5T/5X/5 devices
    • Bank management logic monitors status of each bank
    • Queue-based user interface with reordering scheduler
    • Look-ahead activate, precharge, and auto-precharge logic
    • Parity protection for all stored control registers
    • PHY interface based on DFI 5.1 standard
    Block Diagram -- LPDDR5T / LPDDR5X / LPDDR5 Controller
  • eFPGA Soft IP
    • These eFPGA IP cores offer designers the flexibility to tailor resources to their application requirements, available as either Soft RTL or Hard GDSII IP.
    • Our standard-cell-based approach facilitates rapid porting to new process geometries or variants, including industrial and rad-hard grade versions.
    Block Diagram -- eFPGA Soft IP
  • Sleep Management Subsystem
    • Power-On-Reset
    • Programmable relaxation oscillator
    • Low Power Comparator
    Block Diagram -- Sleep Management Subsystem
  • Power Management Subsystem
    • The agilePMU Subsystem is an efficient and highly integrated Power Management Unit for SoCs/ASICs.
    • Featuring a Power-On-Reset (POR), multiple Low Drop-Out (LDO) regulators, and an associated reference generator.
    • The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities.
    Block Diagram -- Power Management Subsystem
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