IP for Samsung
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eDP RX PHY - 14 nm
- The eDP RX PHY IP is a cost-effective and low-power solution that includes IO pads and ESD structures.
- With extensive built-in self-test features, including loopback and scan, it ensures robust functionality and easy verification.
- This hardmacro supports the eDP RX v1.4b and v1.5a standard and is commonly used for connecting a timing controller (TCON) to a host processor.
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Intra-Panel TX PHY - 28nm, 14nm, 8nm
- The Intra-panel TX PHY IP is an advanced chip-on-glass (ACOG) and chip-on-film (COF) transmitter embedded into the timing controller for TFT-LCD panels.
- This technology enables a single chip to support multiple display interfaces, reducing system costs and complexity.
- It also provides higher data transfer rates, lower power consumption, and compatibility with a wide range of devices.
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PCIe 5.0/6.0 PHY IP - 5nm, 4nm, 2nm
- The PCIe 5.0/6.0 PHY IP consists of hardmacro PMA and PCS compliant with PCIe Base 5.0/6.0 specification.
- This IP offers a cost-effective and low-power solution using FinFET CMOS technology.
- It includes all ESD I/Os and bump pads and supports extensive built-in self test features such as loopback and scan.
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PCle 4.0 PHY IP - 14nm, 8nm, 5nm, 4nm
- The PCIe 4.0 PHY IP consists of hardmacro PMA and softmacro PCS compliant with PCIe Base 4.0 specification.
- This IP offers a cost-effective and low-power solution using FinFET CMOS technology.
- It includes all ESD I/Os and bump pads and supports extensive built-in self test features such as loopback and scan.
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MIPI D-PHY - 28nm, 14nm, 8nm, 5nm, 4nm
- The MIPI D-PHY IP is a hard-macro PHY for CSI RX and DSI TX. IO pads and EDS structures are included.
- In addition, extensive built-in self-test features, such as loopback and scan, are supported.
- It offers a cost-effective and low-power solution.
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MIPI C-PHY - 28nm, 14nm, 8nm, 5nm, 4nm
- The MIPI C-PHY IP is a hard-macro PHY for CSI RX. IO pads and ESD structures are included.
- In addition, extensive built-in self-test features, such as loopback and scan, are supported.
- It offers a cost-effective and low power solution.
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MIPI C-PHY TRx / MIPI D-PHY TRx Combo PHY - 14nm, 8nm, 5nm, 4nm
- The MIPI D-PHY/C-PHY Combo IP is a hard-macro PHY for CSI RX or DSI TX. IO pads and ESD structures are included.
- In addition, extensive built-in self-test features, such as loopback and scan, are supported.
- It offers a cost-effective and low-power solution.
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All Digital Fractional-N RF Frequency Synthesizer PLL in Samsung 14LPP
- Ultra-low jitter, less than 300fs RMS integrated between 12kHz to 20MHz.
- Suitable for many RF applications, including LO, clocks for, ADC, DAC, high-speed PHY
- Small die area (< 0.05 sq mm), using a LC tank oscillator
- Output frequency can be from 1 to 2047 times the input reference, up to 8GHz
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All Digital Fractional-N RF Frequency Synthesizer PLL in Samsung 8LPP
- Fractional Multiplication with frequencies up to 8GHz
- Extremely low jitter (< 300fs RMS)
- Small size (< 0.05 sq mm)
- Low Power (< 7mW)
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All Digital Fractional-N PLL for Performance Computing in Samsung 8LPP
- Fractional multiplication with frequency up to 4GHz
- Low jitter (< 10ps RMS)
- Small size (< 0.01 sq mm)
- Low Power (< 5mW)
- Support for multi-PLL systems
