IP for Samsung
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246
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for Samsung
from 27 vendors
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2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- High Bandwidth Density and Data Rates
- Package Configurability
- Energy Efficiency
- Fully Integrated Solution
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1.8V/3.3V Switchable GPIO with 5V I2C Open Drain and Analog Cells in Samsung 11nm
- A Samsung 11nm Flip-Chip I/O library with dynamically switchable 1.8V/3.3V GPIO with fail-safe capability, 5V I2C / SMBus open-drain cell, 5V OTP cell, 1.8V 3.3V analog cells, and associated ESD.
- A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
- The GPIO cell can be configured as input, output, open source, or open drain with an optional internal 50K ohm pull up or pull down resistor.
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LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
- Compliant for JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
- x16 and x32 channel support
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LPDDR5/4x/4 PHY IP for Samsung 14LPU
- Compliant with JEDEC standards for LPDDR5/4x/4 with PHY standards
- DFI 5.0 Interface Compliant
- Supports 1,2, or 4 ranks
- Multiple frequency states
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LPDDR5T / LPDDR5X / LPDDR5 Controller
- Support for all LPDDR5T/5X/5 devices
- Bank management logic monitors status of each bank
- Queue-based user interface with reordering scheduler
- Look-ahead activate, precharge, and auto-precharge logic
- Parity protection for all stored control registers
- PHY interface based on DFI 5.1 standard
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eFPGA Soft IP
- These eFPGA IP cores offer designers the flexibility to tailor resources to their application requirements, available as either Soft RTL or Hard GDSII IP.
- Our standard-cell-based approach facilitates rapid porting to new process geometries or variants, including industrial and rad-hard grade versions.
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Sleep Management Subsystem
- Power-On-Reset
- Programmable relaxation oscillator
- Low Power Comparator
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Power Management Subsystem
- The agilePMU Subsystem is an efficient and highly integrated Power Management Unit for SoCs/ASICs.
- Featuring a Power-On-Reset (POR), multiple Low Drop-Out (LDO) regulators, and an associated reference generator.
- The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities.
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Sensor Interface Subsystem
- The agileSensorIF Subsystem is an efficient and highly integrated sensor interface for SoCs/ASICs.
- Featuring multiple Analog-to-Digital Converters (agileADC), Digital-to-Analog Converters (agileDAC), low-power programmable analog comparators (agileCMP_LP), and an associated reference generator (agileREF).
- The agileSensorIF Subsystem enables easy interaction with the analog world.
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Low Power BandGap
- The agileREF_LP consists of: A bandgap reference core; A bandgap reference voltage generator (VREF) (Reference current outputs allow for remote reconstruction of an accurate reference voltage.) Bias current generators (IBIAS) (Temperature independent bias current generators)
