Smarter Silicon with Menta eFPGA and HW/SW Co-Design

Value of Hardware-Software Co-Design with Processors + Menta eFPGA 

Traditional processors and microchips provide ease of programmability, but industries such as Space, Communications, Industrial Control, FinTech and many others demand far more — high performance, flexibility, real-time determinism, and mission-grade reliability. These requirements make hardware acceleration not just advantageous, but essential.  

This is where Hardware-Software Co-Design (HW/SW Co-Design) comes in — a methodology that develops hardware and software concurrently and collaboratively to achieve optimal performance, power efficiency, and adaptability. Rather than treating hardware and software as isolated domains, HW/SW Co-Design recognizes them as complementary layers of a unified system, where functionality can be intelligently partitioned between software running on processors and hardware implemented in reprogrammable logic, such as Menta’s 100% standard-cell eFPGA. 

 

At its heart, HW/SW Co-Design is about assigning the right function to the right resource: 

• Software (SW): Great for flexibility, programmability, and control flow. 
• Hardware (HW): Ideal for performance, determinism, and parallel data processing. 

By co-designing them, engineers can offload time-critical or compute-heavy tasks from the CPU into hardware while keeping adaptability in software. Let’s explore several critical benefits of this approach: 

Hardware–Software Synergy for Performance & Flexibility 

By tightly coupling embedded processors (CPU/MCU/SoC) with Menta’s on-chip eFPGA fabric, designers can partition workloads dynamically—offloading compute-intensive, time-critical functions (encryption, signal processing, AI inference, packet inspection, etc.) to hardware while keeping control and orchestration in software. This achieves 10–100× speedups with deterministic latency while preserving software-level programmability. 

 

 Adaptability Without Re-spins 

As standards, algorithms, or security requirements evolve, the software layer can reconfigure the eFPGA at runtime—updating data paths, accelerators, or protocol handlers instantly without altering the ASIC. This enables crypto-agility, protocol agility, and feature agility over the product’s full lifecycle. 

Optimal PPA (Power, Performance, Area) 

Menta’s 100% standard-cell eFPGA integrates seamlessly within the SoC’s existing flow, achieving ASIC-class power and area efficiency—far superior to discrete FPGAs—while allowing the processor to delegate parallel tasks and reduce overall energy per operation. 

Secure and Autonomous Operation 

Because Menta’s eFPGA uses flip-flop configuration memory (no SRAM cells), the system supports secure zeroization in the event of malicious intrusions. Design isolation and hardware authentication is also possible, enabling trusted HW/SW co-execution even in defense or financial-grade applications. 

Lifecycle & Ecosystem Benefits 

HW/SW Co-Design with Menta eFPGA provides a future-proof architecture—the software defines behavior, the eFPGA enforces it in hardware, and both evolve together. This shortens development cycles, improves ROI, and extends ASIC lifespan across multiple product generations and markets. 

How do I decide what software applications to accelerate in hardware? 

To decide which software functions to accelerate in hardware, start by profiling your application to identify performance bottlenecks—functions that consume most of the execution time or limit throughput. Focus on tasks that are compute-intensive, highly parallel, and latency-sensitive, such as linear algebra, cryptography, packet processing, AI inference, or digital signal processing. These are ideal for hardware because they benefit from deterministic, pipelined execution and avoid software overhead.  

Next, evaluate the stability of each algorithm and target evolving workloads that will change frequently, such as, encryption standards, AI models, cryptography, or communication protocols. All of these fit perfectly into Menta’s eFPGA architecture, where they can be reconfigured post-silicon. 

It’s also essential to quantify the impact of hardware acceleration—focus on algorithms that deliver over 10× performance gains, exploit parallel and deterministic execution, and achieve significant efficiency improvements when implemented in hardware. 

 

What are common functions that benefit from HW/SW Co-Design? 

Security & Cryptography 

Why: Algorithms are computationally heavy, latency-sensitive, and evolve over time — perfect for reconfigurable hardware acceleration. Here are a few examples: 

• Post-Quantum Cryptography (PQC) algorithms — hash-based signatures, lattice operations, XMSS (see design example below), Kyber, Dilithium 
• Symmetric/Asymmetric crypto — AES, SHA-2/3, RSA, ECC 
• Key-management and zeroization engines 
• Rolling encryption or hardware root-of-trust functions 
• Tamper detection and side-channel attack mitigation 

Menta’s eFPGA architecture inherently supports hardware obfuscation, as all configuration data and security secrets are erased upon power-down, leaving only a neutral matrix of standard logic cells. This makes it virtually impossible for adversaries to reverse-engineer or extract sensitive IP from the silicon. 

 Signal & Data Processing 

Why: These workloads involve repetitive, deterministic math that maps efficiently to parallel hardware pipelines. 

• Filters (FIR, IIR, Kalman) 
• Convolutions and FFTs 
• DGEM / Matrix multiply / Linear algebra 
• MAC (Multiply-Accumulate) accelerators 
• Adaptive filtering and modulation/demodulation 
• Radar, sonar, and waveform correlation 

AI / Machine Learning 

Why: ML kernels require massive parallelism and often need to be updated as models evolve. 

• Convolutional and recurrent neural network layers 
• Activation, normalization, pooling 
• Quantization / dequantization and data packing 
• Sparse matrix and vector math acceleration 

Networking & Communications 

Why: Network data paths require deterministic throughput with protocol flexibility. 

• Packet parsing and classification 
• Checksum and CRC acceleration 
• Encryption / decryption for VPN or 5G links 
• Forward Error Correction (FEC), Reed-Solomon, LDPC 
• Time-sensitive networking (TSN) scheduling and shaping 

Storage, Memory & Compression 

Why: Data movement and protection dominate latency and power — perfect for near-data acceleration. 

• Compression / decompression (LZ, GZIP, Brotli) 
• ECC engines for SSDs, DIMMs, NVRAM 
• Wear-levelling and error correction 
• Data hashing, deduplication, and secure erase 

Industrial, Automotive & Edge Control 

Why: Real-time control loops and sensor fusion need deterministic response but algorithmic adaptability. 

• Motor control algorithms (FOC, PID, PWM modulation) 
• Sensor fusion for robotics / ADAS 
• Predictive maintenance signal analytics 
• Dynamic protocol translation (CAN, EtherCAT, TSN) 

Aerospace & Defense 

Why: Mission-specific adaptability and long lifecycle hardware demand reconfigurable, secure logic. 

• Crypto-agile communication modules 
• Radar/EO-IR signal chains 
• Electronic warfare and waveform agility 
• Secure boot, authentication, and key management 

How do I get started? What tools and solutions exist today that support this? 

It is easy to get started. There are several tools available today that do everything from profiling your software algorithms and porting them to hardware and creating custom instructions to call those newly accelerated functions.  Let’s explore a few: 

Siemens EDA‘s Catapult™ HLS design tools integrate seamlessly with Menta’s customizable eFPGA IP, enabling designers to move rapidly from SystemC or C++ descriptions to optimized hardware implementations. Menta’s standard-cell eFPGA allows full customization of the programmable fabric—including logic blocks, clocks, memory, ALUs, and interfaces—on any process node, supporting a wide range of SoC applications that demand post-silicon flexibility. This collaboration delivers a faster, more adaptable design flow where algorithms can be quickly transformed into hardware accelerators and later updated in the field, ideal for evolving consumer, industrial, automotive, and wireless systems. 

Menta’s technology partnership with Andes Technology, a premier RISC-V CPU supplier, enables direct integration of Menta’s eFPGA into the AndesCore™ processor families. This collaboration enables in-field customization of RISC-V instruction set architectures (ISAs), allowing designers to add or modify hardware instructions dynamically for specific acceleration needs without breaking software compatibility. By combining Andes’ ACE (Andes Custom Extension™) and COPILOT toolchain with Menta’s reconfigurable eFPGA fabric, the partnership delivers a powerful HW/SW co-design platform that extends processor functionality post-silicon—empowering continuous innovation, performance optimization, and differentiation across applications such as AI, 5G, and domain-specific computing. 

Codasip Studio’s processor design automation tools allows designers to add new instruction sets and microarchitectural enhancements directly in the field, extending processor capabilities long after tapeout. By implementing custom instructions in Menta’s co-extended eFPGA cores, SoC developers can achieve significant performance gains in applications such as cryptography, DSP, and AI without major silicon cost. The joint solution includes an SDK with toolchains, libraries, and documentation, empowering developers to maintain peak performance and adaptability across product lifecycles—ushering in a new era of reconfigurable, RISC-V–based computing architectures. 

New tools are constantly emerging with compelling solutions. Take for example, Rise Design Automation provides a high-abstraction design and verification platform that elevates hardware development beyond traditional RTL, supporting multi-language front ends (SystemC, C++, SystemVerilog), advanced synthesis/analysis engines, generative AI assistance, and rapid derivative product cycles. When paired with Menta eFPGA IP, this combination delivers a powerful synergy—boosting productivity, preserving flexibility, and supporting rapid emergence of differentiated, deployable systems. 

Are there real world examples of systems deploying HW/SW Co-Design? 

Yes, let’s explore two real world examples: 

Crytpo-Agility for long-lasting IC security 

PQSecure Technologies provides hardware acceleration solutions for the XMSS (eXtended Merkle Signature Scheme) algorithm through hardware/software co-design and dedicated IP cores—optimized especially for embedded systems incorporating eFPGA technology. As shown below, this co-design approach dramatically improves the performance and efficiency of XMSS operations compared to pure software implementations in typical edge IoT applications. By selectively running certain components on the processor, it can also reduce hardware requirements by up to 25% relative to a fully hardware-based design. 

 

The hardware accelerator features a SHA-3 engine compliant with NIST FIPS 202, supporting instruction queuing, DMA access, state storage and loading, and direct output-to-input chaining. This enables highly efficient execution of any cryptographic algorithm built upon SHA-3, delivering exceptional performance and throughput. Because the design is scheme-agnostic, it provides strong portability across cryptographic frameworks, making it easily adaptable to various applications. Supported schemes include XMSS, LMS, SLH-DSA, ML-KEM, and ML-DSA, with a DPA-protected variant also available. In addition, SHA-256 and SHA-512 accelerator options are offered for broader algorithmic coverage. 

Digital Printing Security  

This use case illustrates the power of HW/SW Co-Design when combining a RISC-V processor with Menta’s embedded FPGA (eFPGA). In modern printers, the process of rasterizing color images and embedding imperceptible security signatures—through hashing, dithering, and cryptographic modulation—is computationally demanding. Performing these steps purely in software introduces latency and limits throughput. By offloading these repetitive, math-heavy operations into custom RISC-V instructions implemented in Menta’s eFPGA, the system can perform cryptographic hashing, linear feedback shift register (LFSR) dithering, and pixel-level modulation in hardware—directly within the rendering pipeline. This tight HW/SW integration transforms a multi-loop software routine into a single extended instruction, drastically reducing CPU load and accelerating secure image generation in real time. 

Beyond print security, this co-design approach exemplifies the broader value of eFPGA-enabled processors. The ability to create custom instructions in hardware—while maintaining software control—enables continuous adaptability to new algorithms, security standards, and performance demands without respinning silicon. In the printing example, the same eFPGA fabric could later be reconfigured for laser-control logic, image compression, or new watermarking schemes, ensuring long-term product evolution. Menta’s standard-cell eFPGA makes this flexibility native to the SoC, bridging software agility with deterministic hardware performance—precisely the kind of design paradigm driving the next generation of intelligent, secure, and adaptable embedded systems. For more details on this, visit Essential eFPGA Resources and Tools @ Menta.  

Summary 

HW/SW Co-Design represents a transformative shift in how system architects build high-performance, adaptable, and secure silicon. By tightly integrating processors with Menta’s 100% standard-cell eFPGA, designers can dynamically partition workloads—keeping flexibility in software while offloading time-critical, compute-heavy functions to reprogrammable hardware. This approach enables 10–100× performance improvements, ASIC-class efficiency, and the ability to evolve post-silicon without costly redesigns. Whether it’s cryptography, AI inference, signal processing, or industrial control, HW/SW Co-Design delivers deterministic performance, real-time adaptability, and long-term ROI across industries where speed, reliability, and security are paramount. 

Today, a growing ecosystem of tools—from Siemens Catapult HLS and Andes ACE/COPILOT, to Codasip Studio and Rise Design Automation—makes it easier than ever to bring this vision to life. These solutions enable rapid creation of custom instructions, automated hardware generation from C++ or SystemC, and seamless mapping of algorithms into Menta’s eFPGA fabric. Real-world use cases such as PQSecure’s XMSS acceleration and digital print security systems demonstrate how HW/SW Co-Design can deliver hardware-level performance with software-defined flexibility. Together, Menta’s eFPGA and modern co-design methodologies are redefining how engineers build intelligent, crypto-agile, and upgradeable silicon for the future. 

About Menta 

Menta, a pioneering leader in embedded FPGA (eFPGA) technology with over 15 years of proven success, delivers 100% standard-cell, third-party embedded FPGA IP for SoC, ASIC, and ASSP designs. As the only pure-play eFPGA provider offering silicon-proven, synthesis-free IP, Menta empowers semiconductor designers to adapt post-production — enabling rapid updates for bug fixes, customer-specific customizations, evolving standards, or enhanced security. 

Our cutting-edge IP is delivered with the Origami toolchain, a seamless solution that generates bitstreams directly from RTL, streamlining design and accelerating time-to-market. Trusted by global semiconductor leaders, Menta transforms chips into agile, future-proof platforms — redefining what’s possible in silicon design. 

Want to learn more? Contact us at   info@menta-efpga.com