Security IP
Security IP cores are critical components designed to protect embedded systems from cyber threats by providing encryption, authentication, and secure communication. These cores enhance the security of devices by integrating advanced features like Crypto Accelerator IP, which accelerates cryptographic algorithms, and DPA and FIA Countermeasures IP, which safeguard against side-channel attacks. Inline Memory Encryption IP ensures that sensitive data stored in memory is encrypted in real-time, while Quantum Safe Cryptography IP prepares devices for future-proof security against quantum computing threats. Root of Trust IP establishes a secure foundation for boot processes, and Security Protocol Engine IP manages secure communication protocols for reliable, encrypted data transfer.
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1-port Receiver/Transmitter HDCP 2.3 on DisplayPort 1.4/2.0 ESM (generation 3)
- The HDCP 2.3 Embedded Security Modules (ESMs) on DisplayPort are autonomous modules that provide designers with a complete and robust transmitter (TX) or receiver (RX) implementation of the HDCP 2.3 content-protection technology over DisplayPort wired connections, including USB Type-C/USB 3.1.
- This solution helps designers shorten development cycles and fully meet the stringent compliance and robustness requirements of the DCP LLC licensing authority.
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HDCP Authentication Software Stack
- The High-bandwidth Digital Content Protection (HDCP) Authentication Software Stack implements HDCP capability in a Trilinear DisplayPort interface (transmitter or receiver IP core) or the Trilinear HDCP Encryption-Decryption Engine core.
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HDCP Encryption-Decryption Engine
- Real-time encryption/decryption
- 8k compression available for select applications
- Low gate count and low latency implementation
- Supports HDCP 1.3 and 1.4
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Hardware Security Module
- GRHSM is an isolated system-on-chip (SoC) that can be used as a subsystem in a larger SoC design to implement a hardware security module or otherwise provide security functions to the larger system.
- Use cases include crypto key storage, boot authentication, supervision, and offloading of cryptographic functions.
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AES core
- Implemented according to the FIPS 197 documentation.
- Also available in CBC, CFB and OFB modes.
- Key size of 128, 192 and 256 bits.
- Both encryption and decryption supported.
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SHA-1 Processor
- Suitable for data authentication applications.
- Fully synchronous design.
- Available as fully functional and synthesizable VHDL or Verilog soft-core.
- Xilinx and Altera netlist available for various devices.
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MD5 Processor
- RFC 1321 compliant.
- Suitable for data authentication applications.
- Fully synchronous design.
- Available as fully functional and synthesizable VHDL or Verilog soft-core.
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Triple DES core
- Implemented according to the X9.52 standard
- Implementation based on NIST certified DES core
- Also available in CBC, CFB and OFB modes.
- 112 or 168 bits keys supported.
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SHA-256 Processor
- This core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (264 – 1) bits. Simple, fully synchronous design with low gate count.
- The OL_SHA256 core is a fully compliant hardware implementation of the SHA-256 algorithm, suitable for a variety of applications.
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SNOW3G Stream Cipher Core
- The Helion SNOW3G core efficiently implements the stream cipher used as the basis for the UEA2 confidentiality algorithm and UIA2 integrity algorithm which provide data security within the 3GPP UMTS and LTE mobile communication standards.
- The core also fully supports the 128-EEA1 confidentiality and 128-EIA1 integrity algorithms which were introduced in 3GPP Specification Release 8, and which are identical to UEA2 and UIA2 respectively.
