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Security IP

Security IP cores are critical components designed to protect embedded systems from cyber threats by providing encryption, authentication, and secure communication. These cores enhance the security of devices by integrating advanced features like Crypto Accelerator IP, which accelerates cryptographic algorithms, and DPA and FIA Countermeasures IP, which safeguard against side-channel attacks. Inline Memory Encryption IP ensures that sensitive data stored in memory is encrypted in real-time, while Quantum Safe Cryptography IP prepares devices for future-proof security against quantum computing threats. Root of Trust IP establishes a secure foundation for boot processes, and Security Protocol Engine IP manages secure communication protocols for reliable, encrypted data transfer.

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Search (522)
Compare 522 Security IP from 77 vendors (1 - 10)
  • Post-Quantum Key Encapsulation IP Core
    • The PQC-KEM is an IP Core for ML-KEM Key Encapsulation that supports key generation, encapsulation, and decapsulation operations for all ML-KEM variants standardized by NIST in FIPS 203.
    • ML-KEM is a post-quantum cryptographic (PQC) algorithm, designed to be robust against a quantum computer attack.
    Block Diagram -- Post-Quantum Key Encapsulation IP Core
  • SHA-3 Crypto IP Core
    • The SHA-3 – secure hash algorithms – crypto engine is a hardware accelerator for cryptographic hashing functions.
    • It is an area efficient and high throughput design and compliant to NIST’s FIPS 202 standard.
    • Additionally it supports all SHA-3 hash functions – SHA-3-224, SHA-3-256, SHA-3-384 and SHA-3-512 – as well as extendable output functions (XOF) – SHAKE-128 and SHAKE-256. 
    Block Diagram -- SHA-3 Crypto IP Core
  • ASCON Authenticated Encryption & Hashing Engine
    • The ASCON-F IP core is a compact, high-throughput hardware engine implementing the lightweight authenticated encryption with associated data (AEAD) and hashing algorithms described in the Ascon v1.2 specification. 
    • A single instance of the ASCON-F IP core can encrypt or decrypt data using the Ascon-128 and Ascon-128a functions or perform Cryptographic hashing Hash per the Ascon-Hash and Ascon-Hasha functions.
    Block Diagram -- ASCON Authenticated Encryption & Hashing Engine
  • SM4 Cipher Engine
    • The SM4 IP core implements a custom hardware accelerator for the SM4 symmetric block cipher, specified in Chinese national standard GB/T 32907-2016, and ISO/IEC 18033-3:2010/Amd 1:2021.
    • Designed for easy integration, the core, internally expanding the 128-bit key, is capable of both encryption and decryption and features a simple handshake input and output data interface.
    Block Diagram -- SM4 Cipher Engine
  • SNOW-V Stream Cipher Engine
    • The SNOW-V IP core implements the SNOW-V stream cipher mechanism, aiming to meet the security demands of modern high-speed communication systems.
    • It conforms to the official SNOW-V mechanism, published in 2019 by the IACR Transactions on Symmetric Cryptology, as an extensive revision of SNOW 3G stream cipher.
    Block Diagram -- SNOW-V Stream Cipher Engine
  • ML-DSA Digital Signature Engine
    • The KiviPQC™-DSA is a hardware accelerator for post-quantum cryptographic operations.
    • It implements the Module Lattice-based Digital Signature Algorithm (ML-DSA), standardized by NIST in FIPS 204.
    • This mechanism realizes the appropriate procedures for securely generating a private/public key pair, digitally signing a message or a data block, and performing digital signature verification. 
    Block Diagram -- ML-DSA Digital Signature Engine
  • ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
    • The KiviPQC™-Box is a hardware accelerator for post-quantum cryptographic operations.
    • It implements both the Module Lattice-based Key Encapsulation Mechanism (ML-KEM) and the Module Lattice-based Digital Signature Algorithm (ML-DSA), standardized by NIST in FIPS 203 and FIPS 204, respectively.
    Block Diagram -- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
  • ML-KEM Key Encapsulation IP Core
    • The KiviPQC™-KEM is a hardware accelerator for post-quantum cryptographic operations.
    • It implements the Module Lattice-based Key Encapsulation Mechanism (ML-KEM), standardized by NIST in FIPS 203.
    • This mechanism realizes the appropriate procedures for securely exchanging a shared secret key between two parties that communicate over a public channel using a defined set of rules and parameters. 
    Block Diagram -- ML-KEM Key Encapsulation IP Core
  • P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
    • Small size: From 70K ASIC gates (at throughput of 18.2 bits per clock)
    • 500 MHz frequency in 90 nm process
    • Easily parallelizable to achieve higher throughputs
    • Completely self-contained: does not require external memory. Includes encryption, decryption, key expansion and data interface
    Block Diagram -- P1619 / 802.1ae (MACSec) GCM/XTS/CBC-AES Core
  • AES-SX Secure Core - High-Throughput AES Core with Advanced SCA/FI Protection for Performance-Critical Systems
    • The High-Performance AES IP core is a fast, silicon-proven cryptographic engine designed for systems with demanding encryption workloads.
    • Built on a 20 S-box parallel architecture, it delivers exceptional AES-128/256 encryption and decryption throughput while supporting standard modes including ECB, CBC, and CTR (excluding GCM, XTS, and CBC-MAC).
    Block Diagram -- AES-SX Secure Core - High-Throughput AES Core with Advanced SCA/FI Protection for Performance-Critical Systems
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