Security IP
Security IP cores are critical components designed to protect embedded systems from cyber threats by providing encryption, authentication, and secure communication. These cores enhance the security of devices by integrating advanced features like Crypto Accelerator IP, which accelerates cryptographic algorithms, and DPA and FIA Countermeasures IP, which safeguard against side-channel attacks. Inline Memory Encryption IP ensures that sensitive data stored in memory is encrypted in real-time, while Quantum Safe Cryptography IP prepares devices for future-proof security against quantum computing threats. Root of Trust IP establishes a secure foundation for boot processes, and Security Protocol Engine IP manages secure communication protocols for reliable, encrypted data transfer.
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Message filter
- Message filters are placed in the middle of a TCP / TLS session to scan application data, and discard unwanted messages and security-issue packets, reducing unnecessary traffic without increasing CPU load or latency.
- Unlike filters by IP address or port, which scan the data content and discard or pass through packets, DPI (Deep Packet Inspection) and other methods tend to cause CPU processing load and packet processing delays.
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SSL/TLS Offload Engine
- Our SSL/TLS engine accelerates and offloads processing for encryption / decryption and authentication in SSL / TLS by combining our TCP offload and crypt engine.
- Since the record layer processing is completely hardware offloaded, the user application can overwhelmingly reduce the CPU load which only needs preparing the data to transfer securely.
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MacSec Verification IP
- Provides Ethernet fully compliant to 802.3-2018 supporting all media independent interfaces for (1/10/25/40/50/100/200/400/800 G)
- Provides MacSec as per IEEE standard 802.1AE-2018 specification
- Supports controlled and uncontrolled ports
- Encodes and decodes MacSeC PDUs
- Protects and validates macSec Pdus using AES-GCM-128 Cipher suites
- Cryptographic protection
- Modification and Addition of MSDU
- Uses configurable secure association key for encryption and authentication
- Supports Vlan and jumbo frames
- Supports Replay protection and ICV Works in tandem with gPTP (IEEE 802.1AS)/ PTP (IEEE 1588)
- Supports controlled and uncontrolled ports
- Encodes and decodes MacSeC PDUs
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SHA-3 Crypto Core
- SHA3 IP is a high-throughput implementation of SHA-3 cryptographic hashing function built-in an area-efficient approach.
- The core can provide all the fixed-length hashing functions provided as part of the SHA-3 standard.
- A common core is available for diverse ASIC & FPGA applications.
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External NAND flash protection, designed to secure stored assets with a local key from PUF
- PUFenc is designed to protect external flash memory and its stored assets.
- The IP provides asset encryption, such as a learning model for AI or firmware for the chip with a local key from the PUF.
- It adds an additional layer of security by avoiding using the global key, which is a shared key among ICs after the chip leaves the manufacturing floor.
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Blockchain Hardware Accelerator
- Wide variety of ECC curves supported (Weierstrass, Edwards, Montgomery, Twisted-Edwards, …)
- Ideal for FPGA/ASIC integration
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TLS Handshake Hardware Accelerator
- RSA, ECC and more
- > 1 GHz in 16nm
- 400-500 MHz on mid-range/high-end FPGA
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Hardware Security Module (HSM) for Automotive
- Secure key provisioning
- Secure key storage
- Secure counter
- Flexible anti-tampering
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DDR Encrypter
- Protect the external memory
- On-the-fly encryption
- Optional authentication
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SM4-XTS Multi-Booster
- ASIC and FPGA
- High throughput
- Scalable solution
