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Video Post Processing IP

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Compare 10 Video Post Processing IP from 6 vendors (1 - 10)
  • BT656 Decoder with Colour-Space Converter
    • Converts BT.656 digital video to 24-bit RGB
    • Integrated 4:2:2 YCbCr to RGB CSC
    • Supports PAL (576i) and NTSC (480i) formats
    • Outputs include field, video syncs and valid
    Block Diagram -- BT656 Decoder with Colour-Space Converter
  • Motion-adaptive Video Deinterlacer IP Core
    • The DEINTERLACER_MA IP Core is a studio quality 24-bit RGB video deinterlacer capable of generating progressive output video at any resolution up to 216 x 216 pixels.
    • The design is fully programmable and supports any desired interlaced video format.
    Block Diagram -- Motion-adaptive Video Deinterlacer IP Core
  • Video Frame Buffer IP Core Rev. 2.0
    • The VID_FRAME_BUFFER (VFB) IP Core is a high-speed multi-format video frame buffer that samples an input video stream and buffers it in an external memory.
    • The VFB is capable of very high-speed operation achieving over 300 MHz on standard FPGA platforms.
    Block Diagram -- Video Frame Buffer IP Core Rev. 2.0
  • Text Overlay Module (OSD)
    • The TXT_OVERLAY IP Core is a highly versatile On Screen Display (OSD) module that allows text and bitmap graphics to be inserted over RGB video.
    • The module supports a wide range of text effects and the programming interface is very simple.
    • Text is written to a character buffer which is mapped (via a bitmap ROM) directly to the display.
    Block Diagram -- Text Overlay Module (OSD)
  • Deep Learning-based Video Super Resolution Accelerator IP
    • DeepField-SR is a fixed functional hardware accelerator IP for FPGA and ASIC, offering the highest computational efficiency for Video Super Resolution.
    • Based on proprietary AI models trained with real world video dataset and fusing spatio-temporal information in multiple frames, DeepField-SR produces superior high resolution video quality and upscales to fit lager displays.
    Block Diagram -- Deep Learning-based Video Super Resolution Accelerator IP
  • High-efficiency, AI-based super resolution IP
    • The AI-SR series IPs offer super resolution solutions for enhancing video quality and pixel resolution, primarily used for post-processing or display applications.
    • Currently consisting of AISR1000 and AISR2000 IPs, this series enables generation or transfer of low-resolution sources for bandwidth reduction and performance improvement, while ensuring high-quality, high-resolution displays at the edge.
    Block Diagram -- High-efficiency, AI-based super resolution IP
  • Cost-efficiency, AI-based noise reduction IP
    • The AI-NR series IPs offer noise reduction solutions for optimizing image quality in low-light or complex lighting conditions.
    • Currently consisting of the AINR1000 and AINR2000 IPs, this series is capable of significantly reducing image noise while preserving rich picture details and color fidelity, providing superior performance for optimizing image quality in low-light or complex lighting conditions.
    • With dynamic noise processing technology, the AINR1000 efficiently handles not only static noise but also motion noise in video, ensuring clear and smooth visuals at all times.
    Block Diagram -- Cost-efficiency, AI-based noise reduction IP
  • Frame Rate Converter for 4K
    • TMC’s FRUC utilizes “MEMC” algorithm optimized by DMNA.
    • Extremely small generations of halo, judder, and artifact on the interpolating frames.
    • 2:2 pull down and 2:3 pull down detections are implemented.
    • Processing functions for motionless section, scrolling ticker, and screen edge are implemented.
    Block Diagram -- Frame Rate Converter for 4K
  • Graphic 2D Accelerator
    • The Graphic 2D Accelerator (G2D) is a specialized DMA dedicated to image manipulation.
  • Flexible Pixel Processor Video IP
    • The PP300 IP, is a flexible Pixel Processor that provides a wide range of processing functions.
    • The PP300 IP offers various system integration options by providing either memory or direct pixel interfaces for input/output pixels.
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