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Video Post Processing IP

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Compare 15 Video Post Processing IP from 5 vendors (1 - 10)
  • Digital Video Anti-aliasing filter IP Core
    • The ALIAS_FILTER IP Core is a fully pipelined anti-aliasing filter for use in digital video applications.
    • The design implements a low pass filter response on the source video in order to alleviate problems such as jagged edges, stepped lines and Moiré interference patterns.
    • This is especially important when downscaling and upscaling video by large factors.
    Block Diagram -- Digital Video Anti-aliasing filter IP Core
  • HD Multi-window Video Processor IP Core
    • This brief specification describes the operation of the HD Multi-window Video Processor (evaluation) IP Core.
    • The IP Core is provided as a netlist in either EDIF, Verilog or VHDL formats.
    Block Diagram -- HD Multi-window Video Processor IP Core
  • BT656 Decoder with Colour-Space Converter
    • Converts BT.656 digital video to 24-bit RGB
    • Integrated 4:2:2 YCbCr to RGB CSC
    • Supports PAL (576i) and NTSC (480i) formats
    • Outputs include field, video syncs and valid
    Block Diagram -- BT656 Decoder with Colour-Space Converter
  • Motion-adaptive Video Deinterlacer IP Core
    • The DEINTERLACER_MA IP Core is a studio quality 24-bit RGB video deinterlacer capable of generating progressive output video at any resolution up to 216 x 216 pixels.
    • The design is fully programmable and supports any desired interlaced video format.
    Block Diagram -- Motion-adaptive Video Deinterlacer IP Core
  • Video Frame Buffer IP Core Rev. 2.0
    • The VID_FRAME_BUFFER (VFB) IP Core is a high-speed multi-format video frame buffer that samples an input video stream and buffers it in an external memory.
    • The VFB is capable of very high-speed operation achieving over 300 MHz on standard FPGA platforms.
    Block Diagram -- Video Frame Buffer IP Core Rev. 2.0
  • Digital Video Overlay Module
    • The TXT_OVERLAY IP Core is a highly versatile On Screen Display (OSD) module that allows text and bitmap graphics to be inserted over RGB video.
    • The module supports a wide range of text effects and the programming interface is very simple.
    • Text is written to a character buffer which is mapped (via a bitmap ROM) directly to the display.
    Block Diagram -- Digital Video Overlay Module
  • Text Overlay Module (OSD)
    • The TXT_OVERLAY IP Core is a highly versatile On Screen Display (OSD) module that allows text and bitmap graphics to be inserted over RGB video.
    • The module supports a wide range of text effects and the programming interface is very simple.
    • Text is written to a character buffer which is mapped (via a bitmap ROM) directly to the display.
    Block Diagram -- Text Overlay Module (OSD)
  • Warping Engine IP Core
    • TES Warping Engine is a specialized IP core for arbitrary high-performance re-mapping of bitmaps from memory to memory.
    • Applications are for example pre-warping for projection on head-up displays or fisheye-correction of camera images.
    • The IP core adapts to different bus interfaces like AMBA APB and AHB/AXI as well as the Altera Avalon bus interface at different bus width (e.g. 32, 64, 128 bits).
    Block Diagram -- Warping Engine IP Core
  • Deep Learning-based Video Super Resolution Accelerator IP
    • DeepField-SR is a fixed functional hardware accelerator IP for FPGA and ASIC, offering the highest computational efficiency for Video Super Resolution.
    • Based on proprietary AI models trained with real world video dataset and fusing spatio-temporal information in multiple frames, DeepField-SR produces superior high resolution video quality and upscales to fit lager displays.
    Block Diagram -- Deep Learning-based Video Super Resolution Accelerator IP
  • Perceptual Video Quality Optimization IP
    • Fully hardwired IP
    • High performance
    • Codec-agnostic
    • Frame based pre-processor
    Block Diagram -- Perceptual Video Quality Optimization IP
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