IP Catalog > Automotive IP

Automotive IP

Automotive IP cores support a range of protocols critical to automotive applications, including CAN IP, CAN XL IP, CAN-FD IP, FlexRay IP, LIN IP, Safe Ethernet IP, and SafeSPI IP. CAN IP and CAN-FD IP facilitate reliable in-vehicle communication, while CAN XL IP extends bandwidth for high-performance data transfer. FlexRay IP is used for high-speed, fault-tolerant communication in safety-critical systems, and LIN IP supports cost-effective communication in simpler applications. Safe Ethernet IP and SafeSPI IP ensure secure and fault-tolerant data transmission, meeting stringent automotive safety standards.

Explore our vast directory of Automotive IP cores below.

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Search (81)
Compare 81 Automotive IP from 28 vendors (1 - 10)
  • DMA Unit
    • The DMU signals to the attached DMA Controller (DMA request) when there is a newly received message available at one of the attached M_CAN's Rx FIFOs respectively when there is the possibility to load a new Tx message into the M_CAN's Tx FIFO/Queue.
    • The DMA controller then autonomously transfers the received message from the M_CAN's Message RAM to the System Memory or the message to be transmitted from the System Memory to the M_CAN's Message RAM.
    Block Diagram -- DMA Unit
  • Timestamping unit
    • Supports DMA transfers between M_CAN Message RAM and System Memory
    • Up to sixteen 32-bit timestamps supported by TSU
    • On reception or transmission of sync messages by the attached M_CAN, the TSU captures the actual value of its internal 32-bit timestamp counter and stores it to one of its timestamp registers.
    Block Diagram -- Timestamping unit
  • Generic timer IP
    • Enables real-time control loops
    • Deterministic multi-threaded architecture (8 threads per RISC unit)
    • Programmability (special purpose RISC/ALU)
    • Scalable and configurable architecture
    Block Diagram -- Generic timer IP
  • Protocol controller IP for Classical CAN / CAN FD / CAN XL
    • The X_CAN is the new CAN Communication Controller IP supporting CAN XL protocol.
    • It can be integrated as part of a SoC. It is described in VHDL on RTL level, prepared for synthesis.
    • The X_CAN performs communication according to ISO11898-1:2015 and CiA610-1.
    Block Diagram -- Protocol controller IP for Classical CAN / CAN FD / CAN XL
  • Protocol controller IP for CAN / CAN FD
    • The M_CAN module is the new CAN Communication Controller IP-module that can be integrated as stand-alone device or as part of an ASIC.
    • It is described in VHDL on RTL level, prepared for synthesis. The M_CAN performs communication according to ISO 11898-1:2015. Additional transceiver hardware is required for connection to the physical layer.
    Block Diagram -- Protocol controller IP for CAN / CAN FD
  • xSPI/SPI Verification IP
    • Compliant to SPI Specification 512Mbit(64Mbyte) 3.0V SPI FLASH MEMORY S25FL5122
    • Compliant with JEDEC JESD251A expanded serial peripheral interface specification with the help of JEDEC JESD216D-01 SFDP specification.
    • Supports connection to any SPI Memory and SPI Master IP communicating with a CYPRESS spi flash memory model.
    • Supports configurable timing parameters and multi-slave configurations.
    Block Diagram -- xSPI/SPI Verification IP
  • IEEE 802.1AS Software Stack
    • The IEEE 802.1AS software stack implements the Timing and Synchronization protocol for time-sensitive applications over bridged and wireless networks.
    • Based on a profile of the Precision Time Protocol (PTP) as defined in IEEE 1588, 802.1AS provides precise synchronization of clocks across all network devices, enabling accurate time distribution for Time-Sensitive Networking (TSN) and other real-time applications.
    Block Diagram -- IEEE 802.1AS Software Stack
  • CAN 2.0/CAN FD IP core
    • The IP is compliant to the new ISO 11898-1:2015 standard, supporting both standard CAN and CAN FD. 
    • The IP is available for most Xilinx, Altera, Lattice and Microsemi FPGA devices, supporting native bus interfaces like AXI, Avalon and APB. Processor integration is available for SOC type of FPGAs.
    Block Diagram -- CAN 2.0/CAN FD IP core
  • UniPro℠ Controller IP Core
    • The UniPro Controller IP core is fully compliant with the UniPro specification version 1.6 and supports the physical adapter layer of the M-PHY® specification.
    • MIPI UniPro is a high-performance, chip-to-chip, serial interconnect bus for mobile applications. Designed to support up to 5Gbps per data lane, it is scalable from one to four bidirectional lanes.
    Block Diagram -- UniPro℠ Controller IP Core
  • Host / device LIN controller IP
    • The LIN Controllers IP– Local Interconnect Network Controllers IPs are compliant to LIN 2.0, 2.1 & 2.2A Specifications. Backward compliant to LIN 1.3 Specification as well.
    • These can be integrated into systems through various simple AMBA-APB, AMBA-AHB or SRAM like interfaces that require LIN connectivity commonly used in automotive and industrial applications.
    Block Diagram -- Host / device LIN controller IP
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