Embedded Memories IP

The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 1Kbyte (16(bit per word) x 8(words per page) x 64(pages)) with single-bit output data and parallel write data in one word.
Write EEPROM page data comes to input di<15:0> and write process execute if signal wr=“1”.

The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 1024 bits (16(bit per word) x 2(word per page) x 32(page)), which is organized as 32 pages of 2 words by 16 bit with single-bit output data and parallel write data.
Data writing in EEPROM consists of 2 phases - erasing and writing.

The block is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 512 bits (16(bit per word) x 2(word per page) x 16(page)), which is organized as 16 pages of 2 words by 16 bit with single-bit output data and parallel write data.
Write EEPROM page data comes to input D0<15:0> and write by words to latch through the signal SAMPLE, while the signal write in a state of «1». The address of a word written down in latches is defined by two low bits of the bus adr_bl<1:0>.

Supports high temperature and long retention life time for severe automotive requirement
Low power in Program/Erase operation for power critical applications
Requires few (2~3) additional masks
No change to SPICE model of Standard CMOS process, for re-using existing design and IP

Supports high temperature and long retention life time for severe automotive requirement
Low power in Program/Erase operation for power critical applications
Requires few (2~3) additional masks
No change to SPICE model of Standard CMOS process, for re-using existing design and IP

Supports high temperature and long retention life time for severe automotive requirement
Low power in Program/Erase operation for power critical applications
Requires few (2~3) additional masks
No change to SPICE model of Standard CMOS process, for re-using existing design and IP

Supports high temperature and long retention life time for severe automotive requirement
Low power in Program/Erase operation for power critical applications
Requires few (2~3) additional masks
No change to SPICE model of Standard CMOS process, for re-using existing design and IP

Ultra-low voltage logic designs using adaptive body biasing demand dense SRAM solutions which fully integrate in the ABB aware implementation and sign-off flow of the Racyics® ABX Platform solution.
The Racyics® Single Rail SRAM supports ultra-low voltage operation down to 0.55 V where logic designs with Minimum-Energy-Point are implemented.

Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB