Embedded Memories IP

Compare 2,205 Embedded Memories IP from 52 vendors (1 - 10)

Embedded CMOS Flash memory IP with sector/chip Erase and byte Program capability
- SuperFlash technology
- CMOS compatible
- Up to 500K cycle endurance
LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
- Compliant for JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
- x16 and x32 channel support
LPDDR5X/5/4X/4 combo PHY at 7nm
- Compliant with JEDEC JESD209-5B for LPDDR5X/5/4X/4 with PHY standards
- Delivering up to 8533Mbps
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
Low Power Memory Compiler - 1-Port Register File Compiler - GF 22nm FDX
- Specifically designed for ultra-low power applications, this memory leverages body biasing to dramatically reduce power consumption.
- Compatible with industry Adaptive Body Biasing IP for PVT and aging compensation
- Body Biasing functionality (up to +1.3V / -1.5V) to reduce leakage or increase speed at the same power
Low Power Memory Compiler - Single Port SRAM - GF 22nm FDX
- Silicon proven Single Port SRAM compiler for GF22 FDX - Memory optimized for low power and supports body biasing.
Ultra High-Speed Cache Memory Compiler - 2-Port Register File - TSMC N3P
- The Ultra High-Speed cache memory is an adaptable, independent, non-coherent cache Intellectual Property (IP) featuring an advanced cache architecture.
- This architecture enhances system performance, scalability, power efficiency, data locality, application responsiveness, cost optimization, and market competitiveness, providing a distinctive business value.
ReRAM NVM in SkyWater 130nm
- Technology: 130nm, SkyWater S130
- Mask Adder: 2
- Supply Voltage: 1.8V Read, 1.8V+3.3/3.6V Program
- Read Access Time: <20nsec
- Operation Temp.: -40°C - 125°C (can be extended to -55°C)
- Capacity: 256 Kbit (can be customized for 128Kbit - 2Mbit)
- Data Bus Width (Read): 32-bit (can be customized to 16-bit to 128-bit)
Low Latency DRAM Synthesizable Transactor
- Supports 100% of Low Latency DRAM protocol standard Low Latency DRAM specifications
- Supports 8 internal banks
- Supports all mode registers programming
- Supports programmable read latency and row cycle time
HIgh-speed & Low latency Search Engine
- tCAM-IP is a high performance, extremely low latency and highly configurable ternary content-addressable memory IP.
- tCAM-IP can make deterministic search at 300MSPS continuously speed with constant latency at 7 clock cycles.
- It can achieve matching/filtering performance at 300,000,000 packets per second over 40G/100G Ethernet.
SPI/EEPROM Verification IP
- Follows EEPROM basic specification as defined in Atmel AT25128A,AT25256A
- EEPROM and Saifun SA25C020 EEPROM
- Supports SPI Modes 0 (0,0) and 3 (1,1)
- Supports 64-byte Page Mode and Byte Write Operation