Embedded Memories IP
Embedded Memories IP csupport various types of memory, including SRAM, ROM, and Flash, offering fast data access, low latency, and low power consumption for embedded systems.
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Embedded Memories IP
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2,210
Embedded Memories IP
from 54 vendors
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ReRAM NVM in SkyWater 130nm CMOS
- Technology: 130nm, SkyWater S130
- Mask Adder: 2
- Supply Voltage: 1.8V Read, 1.8V+3.3/3.6V Program
- Read Access Time: <20nsec
- Operation Temp.: -40°C - 125°C (can be extended to -55°C)
- Capacity: 256 Kbit (can be customized for 128Kbit - 2Mbit)
- Data Bus Width (Read): 32-bit (can be customized to 16-bit to 128-bit)
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Ultra High-Speed Cache Memory Compiler
- Up to 3.4 GHz operation in N3P process
- Cache size up to 16 Kb
- 4 – 64-bit word width
- Configurable way associativity
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LPDDR5X/5/4X/4 combo PHY at Samsung SF5A
- Compliant for JEDEC standards for LPDDR5X/5/4X/4 with PHY standards
- DFI 5.1 specification PHY Interface Compliant
- Support up to 4 ranks
- x16 and x32 channel support
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CodaCache® Last Level Cache IP
- Standalone IP
- 1.2 GHz frequency in 16FF+TT process
- Protocol interoperability: AMBA AXI 4
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Next Generation Flash device enabling small size, low power and direct connection with digital circuit which opens up new possibiities
- small size
- low power
- direct connection with digital circuit
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LPDDR5X/5/4X/4 combo PHY at 7nm
- Unbeatable performance-driven and low-power-driven PPA
- Ultra-low read/write latency with programmable PHY boundary timing
- Channel equalization with FFE and DFE
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Single Rail SRAM GLOBALFOUNDRIES 22FDX
- Single port SRAM compiler based on Racyics® R188 logic memory cell with dual-well architecture
- Supply voltage 0.55 V to 0.8 V enabled with Racyics® ABB
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Dual-Rail SRAM Globalfoundries 22FDX
- Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
- Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB
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eTCAM (Embedded Ternary Content Addressable Memory IP
- One cycle operation latency (without priority encoder)
- Valid Bit per entry to reduce power
- Valid Bit reset in one cycle support
