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Input/Output Controller IP

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Compare 9 Input/Output Controller IP from 7 vendors (1 - 9)
  • SDIO/SD Memory/MMC Slave Controller
    • Compatible with SD/SDIO specification 2.0 with 1 and 4 bit data transfer.
    • Provides SD interface to peripheral or memory device through a simple address/data interface.
    • Support SD, SPI and optional MMC bus protocol.
    • Support for both standard capacity and high capacity (SDHC) memory cards.
    Block Diagram -- SDIO/SD Memory/MMC Slave Controller
  • General Purpose Input / Output Controller (GPIO)
    • The GPIOmodule is a general purpose input/output controller, offering some unique features that eases system integration and use.
    • Each GPIO port can be configured for input, output or bypass mode. Output data can be set in one access or single or multiples bits can be set or cleared.
    Block Diagram -- General Purpose Input / Output Controller (GPIO)
  • APB General Purpose IO (w/ interrupt)
    • The APB GPIO is a configurable module allowing the use of up to 32 scalable I/O lines.
    • If more than 32 I/Os are required, more than one GPIO module may be instantiated.
    • Each line can be configured independently resulting in a very useful I/O application.
    Block Diagram -- APB General Purpose IO (w/ interrupt)
  • Intel 8255A Functional Equivalent Programmable Peripheral Interface
    • The DB8255A Programmable Peripheral Interface core is a full function equivalent to the Intel 8255A / 82C55A and Intersil 82C55A devices.
    • The DB8255A implements a general-purpose I/O interface connecting peripheral equipment to a microprocessor system bus.
    • The core generates 24 programmable I/O lines which are individually programmed in 2 groups of 12 and used in 3 major modes of operation.
    Block Diagram -- Intel 8255A Functional Equivalent Programmable Peripheral Interface
  • PS/2 Keyboard controller, fully configurable
    • PS/2 core is used to communicate with either keyboard or mouse device
    • PS/2 core can be configured to use single or dual connection signals within the same core
    • AHB or WISHBONE SoC Interconnection Rev B compliant interface
    • PS/2 can operate in pooling or interrupt mode
    Block Diagram -- PS/2 Keyboard controller, fully configurable
  • General Purpose I/O controller, fully configurable.
    • Number of general-purpose I/O signals is user selectable and can be in range from 1 to 32. For more I/Os several GPIO cores can be used in parallel
    • All general-purpose I/O signals can be bi-directional (external bi-directional I/O cells are required in this case)
    • All general-purpose I/O signals can be three-stated or open-drain enabled (external three-state or open-drain I/O cells are required in this case)
    • General-Purpose I/O signals programmed as inputs can cause an interrupt request to the CPU
    Block Diagram -- General Purpose I/O controller, fully configurable.
  • Enhanced Multiprotocol Serial Communication Controller
    • Rapid prototyping and time-to-market reduction
    • Design risk elimination
    • Development costs reduction
  • Programmable Peripheral Interface
    • Compatible with industry standard 8255
    • 24 I/O lines individually programmed in 2 groups of 12:
    • 3 major modes of operation
    • Control Word Read-Back Capability
  • Versatile Interface Adapter (VIA)
    • Advanced CMOS process technology for low power consumption
    • Compatible with NMOS 6522 devices
    • Low power consumption
    • Two 8-bit, bi-directional peripheral I/O Ports
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Semiconductor IP