Input/Output Controller IP
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Input/Output Controller IP
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29
Input/Output Controller IP
from 14 vendors
(1
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10)
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xSPI - PSRAM Master
- SPI Protocol:
- AXI4 Slave
- AXI4 DMA Master
- AXI4 – LITE SLAVE
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I3C Host Controller
- Compliant with MIPI I3C Specification V1.0
- Supports up to 12.5 MHz operation using Push-Pull.
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xSPI Master IP | NOR IP
- JESD 251 compliant
- JEDEC SFDP Compliant
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I3C Dual Controller
- Compliant with MIPI I3C Specification (v1.1/v1.1.1)
- Compliant with MIPI I3C HCI Specification (v1.2)
- Supports up to 12.5 MHz operation using Push-Pull
- Open-Drain and Push-pull type transactions
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APB4 General Purpose Input/Output Module
- Compliant with AMBA APB v2.0 Specification
- User-defined number of Bi-directional General Purpose IO
- Automatic synchronisation of General Inputs to Bus Clock
- Each General Output configurable as push-pull or open-drain
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I3C Slave Controller
- Compliant with MIPI I3C Specification V1.0
- Supports up to 12.5 MHz operation using Push-Pull.
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General-Purpose I/O Controller with APB Interface
- User selectable number of GPIO signals from 1 to 32
- All GPIO signals can be bi-directional (external bi-directional I/O cells are required in that case)
- All GPIO signals can be tri-stated or open-drain enabled (external tri-state or open-drain I/O cells are required in that case)
- GPIO signals programmed as inputs can cause an interrupt request to the CPU
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Quad SPI Master IP
- Compliant with AMBA AXI3/4 and AXI4-lite protocols.
- User configurable clock frequency support
- Designed to support all leading NOR FLASH devices.
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I3C Master and Slave Dual Role Controller
- Compliant with the latest version of the MIPI I3C specification
- Legacy I2C
- I3C features
- Low Power
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I3C Prototyping Kit (HDK) Total IP in a Box
- Compliant with MIPI I3C Specification V1.0
- Supports up to 12.5 MHz operation using Push-Pull.
