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Building Blocks IP

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Search (368)
Compare 368 Building Blocks IP from 50 vendors (1 - 10)
  • Radar processing IP suite for Advanced Driver Assistance Systems
    • The eSi-ADAS™ is a suite of radar accelerator IP including a complete Radar co-processor engine, they enhance the overall performance and capabilities of radar  systems for automotive, drone and UAV applications that require fast and responsive situational awareness.
    • The IP has been licensed to some of the leading automotive Tier 1 and Tier 2 suppliers and is in production vehicles.
    Block Diagram -- Radar processing IP suite for Advanced Driver Assistance Systems
  • RGB to ITU-R 601/656 Encoder
    • The DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller (or any LCD display timing & control unit) to a TFT LCD Panel by-way-of a CCIR 601 / CCIR 656 interface.
    Block Diagram -- RGB to ITU-R 601/656 Encoder
  • Power-On Reset - Flexible Threshold (1­-1.3V), Ultra Low Current (100nA) - SilTerra 0.16µm CL160G
    • This macro-cell is an ultra low consumption Power-On Reset (POR) core designed for SilTerra 0.16μm CL160G CMOS technology.
    • The threshold sensing voltage can be configured from 1V to 1.3V (default is 1.15V). A hysteresis of 120mV is added to avoid false reset glitches in noisy supplies.
    Block Diagram -- Power-On Reset - Flexible Threshold (1­-1.3V), Ultra Low Current (100nA) - SilTerra 0.16µm CL160G
  • RAM 8b, 16b, and 32b data widths - TSMC 180nm
    • 8b, 16b, and 32b data widths available.
    • Up to 250MHz clock operation.
    • Read and write data busses may tie for single bus operation.
    • Available production test RTL.
    • VDD 1.6V – 2.0V.
    • Data retention to 0.9V.
    Block Diagram -- RAM 8b, 16b, and 32b data widths - TSMC 180nm
  • XMBus Verification IP
    • Supports XMBus specifications version 0.5.
    • Supports XMBus device types: Master, Slave.
    • Start, repeated start and stop for all possible transfers.
    • Supports 7bit configurable Slave address.
    Block Diagram -- XMBus Verification IP
  • OpenCores Wishbone B3 Verification IP
    • Compliant to OpenCores Wishbone B3 Protocol.
    • Support for all types of Wishbone devices
    • Master
    • Slave
    Block Diagram -- OpenCores Wishbone B3 Verification IP
  • USIM Verification IP
    • Compliant with 3GPP TS 31.102 and ETSI TS 102 221 Specification.
    • Supports USIM interface between Master and Slave.
    • Supports specific command parameters.
    • Supports file structures.
    Block Diagram -- USIM Verification IP
  • UAS VIP
    • Compliant with the USB attached SCSI specification UAS 3, Rev 4b.
    • Compliant with the USB 2.0 specification.
    • Compliant with the USB 3.0/3.1/3.2 specifications.
    • Compliant with the SCSI Architecture Model 6 (SAM-6).
    Block Diagram -- UAS VIP
  • TS5 Verification IP
    • Implemented in native OpenVera, Verilog, SystemC and SystemVerilog.
    • Supported RVM, AVM, VMM, OVM, UVM and non-standard verify env.
    • Supports JEDEC TS5 specifications.
    • Full TS5 Master and Slave functionality.
    Block Diagram -- TS5 Verification IP
  • Trusted Platform Module (TPM) Verification IP
    • Full TPM master device and slave device functionality.
    • Compliant to the Trusted Computing Group (TCG) Trusted Platform Module(TPM) Version 1.1b/1.2 and 2.0 Specification
    • Compliant with TCG PC client-specific TPM Interface Specification (TIS) version 1.2/1.3
    • Hardware Asymmetric Crypto Engine.
    Block Diagram -- Trusted Platform Module (TPM) Verification IP
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