IP for Tower
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eFPGA Soft IP
- These eFPGA IP cores offer designers the flexibility to tailor resources to their application requirements, available as either Soft RTL or Hard GDSII IP.
- Our standard-cell-based approach facilitates rapid porting to new process geometries or variants, including industrial and rad-hard grade versions.
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Custom Regulated High Capacity Charge Pump
- On-Chip Supply Rail Extension
- Extends the headroom and performance range of other on-chip blocks and components
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Super Inductor IP
- High Inductor Q (10 to 50)
- High Inductor Bandwidth (2.5Ghz to 50Ghz)
- Stackable Design
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Revolutionaly Ultra Low Phase Noise RF Amplifier-LNA IP
- Revolutionary Ultra Low Phase Noise operation
- Ultra Low Power Operation
- RF front end sensitivity enhancement
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Revolutionary Ultra Low Phase Noise Driver IP
- Revolutionary Ultra Low Phase Noise operation
- Ultra Low Power Operation
- RF front end sensitivity enhancement
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CC-100IP-PI Power Integrity Enhancement IP
- Occupies the same on chip area as standard DCAPs with at least a 600X effective capacitance increase
- Up to a 36% Dynamic Power and RF Emissions Reduction
- On-Chip Cybersecurity Enhancement
- 25% Reduction in Capacitor ESL
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CC-100IP-RF Analog and RF Sensitivity Enhancement IP
- Enhances the Sensitivity of Analog and RF Frontend Receivers
- Enhances the PSRR od Analog and RF Frontend Receivers
- Occupies the same on chip area as standard DCAPs with at least a 600X effective capacitance increase
- Up to a 36% Dynamic Power and RF Emissions Reduction
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CC-100IP-MB Electric Vehicle Mileage Booster IP
- Extends EV Driving range by 10%
- Extends the driving and Biking Range of Electric Vehicles from 16 to 30 Miles
- Occupies the same on chip area as standard DCAPs with at least a 600X effective capacitance increase
- Up to a 36% Dynamic Power and RF Emissions Reduction
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Hyper-Decoupling Capacitor with a Capacitance Multiplication, Series Inductance Nullification, Cybersecurity Enhancement and an Energy Harvesting capabilities
- Occupies the same on chip area as standard DCAPs with at least a 600X effective capacitance increase
- Up to a 36% Dynamic Power and RF Emissions Reduction
- On-Chip Cybersecurity Enhancement
- 25% Reduction in Capacitor ESL
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I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus
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The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).
The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.
The DB-I2C-MS-APB is a Master/Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.
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