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RISC-V Processor IP

Welcome to the ultimate RISC-V Processor IP hub! Explore our vast directory of RISC-V Processor IP.

RISC-V is an open-source instruction set architecture used to develop custom processors for a variety of applications, from embedded designs to supercomputers.

Unlike proprietary processor architectures, RISC-V is an open-source instruction set architecture (ISA) used for the development of custom processors targeting a variety of end applications.

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Compare 150 RISC-V Processor IP from 34 vendors (1 - 10)
  • 64-bit High Performance Out-of-Order Processor - Out-of-Order, 3/4/6-Wide Decode
    • The UX1000 Series have three different variants: UX1030, UX1040 and UX1060.
    • UX1030 is a 3-wide processor with good performance and smaller power & area; UX1040 is a 4-wide processor with better performance and balanced power & area; UX1060 is a 6-wide processor with even higher performance targeting high-end applications.
    Block Diagram -- 64-bit High Performance Out-of-Order Processor - Out-of-Order, 3/4/6-Wide Decode
  • 32-Bit & 64-Bit High Performance Processor - 9-Stage Pipeline, Dual-issue
    • 900 Series processors include four different classes: N900 (32 bit), U900 (32 bit + MMU), NX900 (64 bit) and UX900 (64 bit + MMU). With MMU, UX900 supports heavyload operating systems such as Linux. 900 Series can be applied to edge computing, data center, networking, etc.
    Block Diagram -- 32-Bit & 64-Bit High Performance Processor - 9-Stage Pipeline, Dual-issue
  • 32-Bit & 64-Bit High Performance Processor - 6-Stage Pipeline, Single-issue
    • 600 Series processors include four different classes: N600 (32 bit), U600 (32 bit + MMU), NX600 (64 bit) and UX600 (64 bit + MMU).
    • With MMU, UX600 supports heavyload operating systems such as Linux. 600 Series can be applied to edge computing, data center, networking, etc.
    Block Diagram -- 32-Bit & 64-Bit High Performance Processor - 6-Stage Pipeline, Single-issue
  • RVA23, Multi-cluster, Hypervisor and Android
    • 64-bit out-of-order 4 wide decode 13-stage CPU core with 128 reordering buffers and 8 functional pipelines
    • Symmetric multiprocessing up to 8 cores
    • Private L2 cache support
    • Level-3 shared cache and coherence support
    Block Diagram -- RVA23, Multi-cluster, Hypervisor and Android
  • High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, and cache coherency
    • SCR7 is a high-performance, silicon-proven, Linux-capable 64-bit RISC-V processor core optimized for applications that demand powerful data processing capabilities.
    • The SCR7 core supports RISC-V standard "I" Integer, "M" Integer Multiplication and Division, "A" Atomic, "C" 16-bit Compressed, "F" Single-Precision Floating-Point, "D" Double-Precision Floating-Point, "B" Bit Manipulation, and "K" Scalar Cryptography extensions.
    Block Diagram -- High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, and cache coherency
  • High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, a VPU, cache coherency, and a hypervisor
    • SCR9 is a high-performance, silicon-proven, Linux-capable 64-bit RISC-V processor core for entry-level server-class applications and personal computing devices.
    • The SCR9 core supports RISC-V standard "I" Integer, "M" Integer Multiplication and Division, "A" Atomic, "C" 16-bit Compressed, "F" Single-Precision Floating-Point, "D" Double-Precision Floating-Point, "V" Vector Operations, "B" Bit Manipulation, and "K" Scalar Cryptography extensions.
    Block Diagram -- High-performance Linux-capable application core with a 12-stage dual-issue out-of-order pipeline, a VPU, cache coherency, and a hypervisor
  • ARC-V RPX Series Functional Safety Processor IP
    • The ARC-V™ RPX-110 series functional safety (FS) processors, which include the RPX-110-FS, RPX-115-FS, RPX-110V-FS, and RPX-115V-FS processors simplify development of high-performance safety-critical applications and accelerate ISO 26262 certification for automotive system-on-chips (SoCs).
    • The Automotive Safety Integrity Level (ASIL) D compliant processors feature a pre-verified dual-core lockstep implementation including an integrated safety monitor.
    • Additionally, they offer the flexibility to operate in an independent “hybrid” mode for ASIL B or non-automotive applications that demand higher performance from the same design.
    Block Diagram -- ARC-V RPX Series Functional Safety Processor IP
  • Custom RISC-V Processor
    • Traditional processors no longer strike the right balance between high performance, energy consumption, and cost.
    • Keysom processors deliver powerful capabilities, optimizing IoT and AI workflows with energy-efficient, small-footprint solutions.
    Block Diagram -- Custom RISC-V Processor
  • High-performance RISC-V CPU
    • Fully compliant with the RVA23 RISC-V specification
    • Comparable PPA to Arm Neoverse V3 / Cortex-X4
    • Standard AMBA CHI.E coherent interface for SoC and chiplet integration
    • Co-architected with Veyron E2 for seamless vector, AI acceleration, and big-little style heterogeneous compute configurations
    Block Diagram -- High-performance RISC-V CPU
  • 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
    • 2 different packages with or without vector: AX46MPV, AX46MP
    • in-order dual-issue 8-stage CPU core with up to 2048-bit VLEN
    • Symmetric multiprocessing up to 16 cores
    • Private Level-2 cache
    • Shared L3 cache and coherence support
    Block Diagram -- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
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