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RISC-V Processor IP

Welcome to the ultimate RISC-V Processor IP hub! Explore our vast directory of RISC-V Processor IP.

RISC-V is an open-source instruction set architecture used to develop custom processors for a variety of applications, from embedded designs to supercomputers.

Unlike proprietary processor architectures, RISC-V is an open-source instruction set architecture (ISA) used for the development of custom processors targeting a variety of end applications.

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Compare 139 RISC-V Processor IP from 31 vendors (1 - 10)
  • 64-bit in-order RISC-V Customisable IP Core
    • Ready for the most demanding workloads, Avispado supports large memory capacities with its 64-bit native data path. With its complete MMU support, Avispado is also Linux-ready, including multiprocessing.
    Block Diagram -- 64-bit in-order RISC-V Customisable IP Core
  • 64-bit Out-of-Order RISC-V Customisable IP Core
    • Ready for the most demanding workloads, Atrevido supports large memory capacities with its 64-bit native data path. With its complete MMU support, Atrevido is also Linux-ready, including multiprocessing.
    Block Diagram -- 64-bit Out-of-Order RISC-V Customisable IP Core
  • ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
    • D23-SE processor core certified by parts 2, 4, 5, 7, 8 and 9 of the standards, meeting the architectural metrics and random hardware fault metrics requirements for ASIL B/D 
    • D23-SE supports split-mode that 2 cores could run independently when split-lock is configured. ECC for memory soft error protection; bus protection to protect bus transaction; core trap status bus interface provides real time information of trap status from core.
    Block Diagram -- ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
  • 8-stage superscalar processor that supports ISO 26262 ASIL (Automotive Safety Integrity Level) -D level functional safety for automotive applications
    • 32-bit in-order dual-issue 8-stage pipeline CPU architecture
    • AndeStar™ V5 Instruction Set Architecture (ISA)
    • 16/32-bit mixable instruction format for compacting code density
    • Advanced low power branch predication to speed up control code
    • Return Address Stack (RAS) to accelerate procedure returns
    Block Diagram -- 8-stage superscalar processor that supports ISO 26262 ASIL (Automotive Safety Integrity Level) -D level functional safety for automotive applications
  • 32-bit Embedded RISC-V Functional Safety Processor
    • The EMSA5-FS is a processor core designed for functional safety.
    • The fault-tolerant processor uses dual or triple instances of the EMSA5, an efficient 32-bit embedded processor IP core implementing the RISC-V Instruction Set Architecture (ISA).
    Block Diagram -- 32-bit Embedded RISC-V Functional Safety Processor
  • Ultra-Low-Power Deeply Embedded RISC-V Processor
    • The BA51 is a highly configurable, low-power, deeply embedded RISC-V processor IP core.
    • It implements a single-issue, in-order, 2-stage execution pipeline and supports the RISC-V 32-bit base integer instruction set (RV32I), or the 32-bit base embedded instructions set (RV32E).
    Block Diagram -- Ultra-Low-Power Deeply Embedded RISC-V Processor
  • Low-Power Deeply Embedded RISC-V Processor
    • The BA53 is a configurable, low-power, deeply-embedded RISC-V processor IP core.
    • It implements a single-issue, in-order, 5-stage execution pipeline, and supports the RISC-V 32-bit base integer instruction set (RV32I), or the 32-bit base embedded instructions set (RV32E).
    Block Diagram -- Low-Power Deeply Embedded RISC-V Processor
  • Simulation VIP for TileLink
    • Channels
    • Drive, sample, and check the signals and operations on channels A and D for TL-UL/TL-UH conformance level and on channels A, B, C, D and E for TL-C conformance level
    • TL-UL
    • Support for TL-UL conformance level including Flow Control Rules, Deadlock Freedom, Request-Response message ordering, Errors and Byte lanes
    Block Diagram -- Simulation VIP for TileLink
  • TileLink Verification IP
    • Compliant with TileLink specification Version 1.8.1.
    • Supports TileLink Master, TileLink Slave, TileLink Interconnect, TileLink Monitor and TileLink Checker.
    • Supports TileLink Uncached Lightweight (TL-UL),TileLink Uncached Heavy weight (TL-UH) and TileLink Cached (TL-C) conformance levels.
    • Supports Cache-coherent shared memory.
    Block Diagram -- TileLink Verification IP
  • TileLink Verification IP
    • Compliant to TileLink specification from SiFive inc.
    • Support for all type of TiLeLink Agents: TileLink Master, TileLink Slave
    • Wide range of strict programmable protocol checks
    • Slave memory data check
    Block Diagram -- TileLink Verification IP
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