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RISC-V Processor IP

Welcome to the ultimate RISC-V Processor IP hub! Explore our vast directory of RISC-V Processor IP.

RISC-V is an open-source instruction set architecture used to develop custom processors for a variety of applications, from embedded designs to supercomputers.

Unlike proprietary processor architectures, RISC-V is an open-source instruction set architecture (ISA) used for the development of custom processors targeting a variety of end applications.

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Compare 144 RISC-V Processor IP from 32 vendors (1 - 10)
  • High-performance RISC-V CPU
    • Fully compliant with the RVA23 RISC-V specification
    • Comparable PPA to Arm Neoverse V3 / Cortex-X4
    • Standard AMBA CHI.E coherent interface for SoC and chiplet integration
    • Co-architected with Veyron E2 for seamless vector, AI acceleration, and big-little style heterogeneous compute configurations
    Block Diagram -- High-performance RISC-V CPU
  • RVA23, Multi-cluster, Hypervisor and Android
    • 64-bit out-of-order 4 wide decode 13-stage CPU core with 128 reordering buffers and 8 functional pipelines
    • Symmetric multiprocessing up to 8 cores
    • Private L2 cache support
    • Level-3 shared cache and coherence support



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    Block Diagram -- RVA23, Multi-cluster, Hypervisor and Android
  • 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
    • 2 different packages with or without vector: AX46MPV, AX46MP
    • in-order dual-issue 8-stage CPU core with up to 2048-bit VLEN
    • Symmetric multiprocessing up to 16 cores
    • Private Level-2 cache
    • Shared L3 cache and coherence support
    Block Diagram -- 64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
  • Superscalar Out-of-Order Execution Multicore Cluster
    • 64-bit out-of-order 4 wide decode 13-stage CPU core with 128 reordering buffers and 8 functional pipelines
    • Symmetric multiprocessing up to 8 cores
    • Level-2 cache and coherence support
    • AndeStar™ V5 Instruction Set Architecture (ISA)
    • 64-bit architecture for memory space over 4GB
    • TAGE Branch predication for highly accurate prediction
    Block Diagram -- Superscalar Out-of-Order Execution Multicore Cluster
  • 64-Bit 8-stage superscalar RISC-V processor
    • 64-bit in-order dual-issue 8-stage pipeline CPU architecture
    • AndeStar™ V5 Instruction Set Architecture (ISA)
    • 16/32-bit mixable instruction format for compacting code density
    • Advanced low power branch predication to speed up control code
    • Return Address Stack (RAS) to accelerate procedure returns
    Block Diagram -- 64-Bit 8-stage superscalar RISC-V processor
  • 8-stage superscalar RISC-V processor
    • The 64-bit AX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP instructions, “B” bit manipulation, and Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions.
    Block Diagram -- 8-stage superscalar RISC-V processor
  • 64-bit Multiprocessor with Level-2 Cache-Coherence
    • 64-bit in-order dual-issue 8-stage pipeline CPU architecture
    • Symmetric multiprocessing up to 8 cores
    • Level-2 cache and cache coherence support
    • AndeStar™ V5 Instruction Set Architecture (ISA)
    Block Diagram -- 64-bit Multiprocessor with Level-2 Cache-Coherence
  • 64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
    • 64-bit in-order dual-issue 8-stage CPU core with up to 1024-bit Vector Processing Unit (VPU)
    • Symmetric multiprocessing up to 8 cores
    Block Diagram -- 64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
  • 64-bit CPU with Modern RISC Architecture, MemBoost and PMA
    • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
    • Floating point extensions
    • DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
    • Andes extensions, architected for performance and functionality enhancements
    • Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
    • 64-bit CPU architecture, enabling software to utilize the memory spaces far beyond 4G bytes imposed by 32-bit CPUs
    Block Diagram -- 64-bit CPU with Modern RISC Architecture, MemBoost and PMA
  • 64-bit CPU Core with Level-2 Cache Controller
    • AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
    • Floating point extensions
    • DSP/SIMD ISA to boost the performance of voice, audio, image and signal processing
    • Andes extensions, architected for performance and functionality enhancements
    • Separately licensable Andes Custom Extension™ (ACE) for customized acceleration
    Block Diagram -- 64-bit CPU Core with Level-2 Cache Controller
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