RISC-V Processor IP
Welcome to the ultimate RISC-V Processor IP hub! Explore our vast directory of RISC-V Processor IP.
RISC-V is an open-source instruction set architecture used to develop custom processors for a variety of applications, from embedded designs to supercomputers.
Unlike proprietary processor architectures, RISC-V is an open-source instruction set architecture (ISA) used for the development of custom processors targeting a variety of end applications.
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RISC-V Processor IP
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Vector-Capable Embedded RISC-V Processor
- The EMSA5-GP is a highly-featured 32-bit RISC-V embedded processor IP core optimized for processing-demanding applications.
- It is equipped with floating-point and vector-processing units, cache memories, and is suitable for concurrent execution in a multi-processor environment.
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Compact Embedded RISC-V Processor
- The BA5x-CM is a feature-rich 32-bit deeply embedded processor.
- Equipped with a floating-point unit and an instruction cache memory and supporting concurrent execution in a multiprocessor environment, it is well-suited to a wide range of edge IoT and similar applications.
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Tiny, Ultra-Low-Power Embedded RISC-V Processor
- The BA5x-TN is a compact, ultra-low power, 32-bit, deeply embedded processor IP core.
- With a two-stage execution pipeline, the processor implements the Embedded variant of the base RV32 ISA (RV32E).
- It uses just 16 general-purpose compressed instructions and omits other resource-demanding extensions.
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Enhanced-Processing Embedded RISC-V Processor
- The BA5x-EP is a highly-featured 32-bit RISC-V embedded processor IP core optimized for complex, processing-demanding applications.
- It is equipped with a floating-point unit and cache memories, supports hardware-level virtualization, and is suitable for concurrent execution in a multi-processor environment.
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Low-Power Embedded RISC-V Processor
- The BA5x-LP is a highly efficient, low-power, 32-bit, deeply embedded processor IP core.
- The two-stage pipeline processor implements either the RV32I or RV32E instruction set.
- It comes pre-configured with the Multiply/Divide (M) and Compressed Instruction (C) extensions, providing a more flexible and capable platform without a significant increase in area or power.
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8-stage dual issue, in-order, superscalar processor with dual vector processing units (1024-bit VLEN/512-bit DLEN)
- New RVA23 support
- New RVV1.0 512-bit vector engine
- New SSCI interface added alongside VCIX
- New instructions and extensions
- New improved memory subsystem
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32-Bit & 64-Bit High Performance Processor - 9-Stage Pipeline, Dual-issue
- 900 Series processors include four different classes: N900 (32 bit), U900 (32 bit + MMU), NX900 (64 bit) and UX900 (64 bit + MMU). With MMU, UX900 supports heavyload operating systems such as Linux. 900 Series can be applied to edge computing, data center, networking, etc.
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32-Bit & 64-Bit High Performance Processor - 6-Stage Pipeline, Single-issue
- 600 Series processors include four different classes: N600 (32 bit), U600 (32 bit + MMU), NX600 (64 bit) and UX600 (64 bit + MMU).
- With MMU, UX600 supports heavyload operating systems such as Linux. 600 Series can be applied to edge computing, data center, networking, etc.
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64-bit High Performance Out-of-Order Processor - Out-of-Order, 3/4/6-Wide Decode
- The UX1000 Series have three different variants: UX1030, UX1040 and UX1060.
- UX1030 is a 3-wide processor with good performance and smaller power & area; UX1040 is a 4-wide processor with better performance and balanced power & area; UX1060 is a 6-wide processor with even higher performance targeting high-end applications.
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64-bit application processor for energy-efficient computation
- Dubhe-80 processor features a 9+ stage, 3-issue, out-of-order pipeline, fully compliant with a rich set of RISC-V extensions of RV64GCBH_Zicond_Zicbom_Zicboz_Zicbop.
- With a score of 8.5 SPECInt2006/GHz, Dubhe-80 is designed for mobile, desktop, AI, and automotive applications that require highly energy-efficient computation.