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DSP Core IP

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Search (58)
Compare 58 DSP Core IP from 20 vendors (1 - 10)
  • 16-bit fixed-point general purpose DSP
    • The iniDSP is designed for system-on-chip applications. A highest degree of reusability is guaranteed by having a 100% technology independent design, synchronous and structured design rules and software support.
    • This core is based on the architecture of the CD2450A from Clarkspur Inc.
    Block Diagram -- 16-bit fixed-point general purpose DSP
  • Ultra-low-power Processor based on RISC-V Architecture
    • The icyflex-V processor is a new ultra-low-power core based on the RISC-V 32-bit ISA, compatible with off-the-shelf open-source and/or proprietary programming tools.
    • This new development represents a cost effective yet performing alternative to proprietary cores for next-generation ultra-low-power system-on-chip developments.
    • The core was optimized for performance, code density and power consumption and delivers up to 3.2 CoreMark/MHz while consuming as low as 14 uA/MHz in TSMC 55 nm low-power process.
    Block Diagram -- Ultra-low-power Processor based on RISC-V Architecture
  • Radar processing IP suite for Advanced Driver Assistance Systems
    • The eSi-ADAS™ is a suite of radar accelerator IP including a complete Radar co-processor engine, they enhance the overall performance and capabilities of radar  systems for automotive, drone and UAV applications that require fast and responsive situational awareness.
    • The IP has been licensed to some of the leading automotive Tier 1 and Tier 2 suppliers and is in production vehicles.
    Block Diagram -- Radar processing IP suite for Advanced Driver Assistance Systems
  • Audio and control DSP
    • Quad 16x16 MACs
    • Dual 32x32 MACs
    • 4-way VLIW
    Block Diagram -- Audio and control DSP
  • Baseband processor
    • The Ceva-BX2 baseband processor IP handles both signal-processing and control workloads with up to 16 GMACs per second performance and high-level-language programming.
    • It supports a range of integer and floating-point data types for a wide range of baseband applications like 5G PHY control, and exploits a high degree of parallelism, but with remarkably compact code size.
    • Optimized high-speed interfaces expedite connection to other Ceva cores or to accelerators.
    Block Diagram -- Baseband processor
  • Tensilica HiFi 1 DSP
    • Cycle and energy efficient for Bluetooth and Bluetooth Low Energy (BLE) codecs for speech and music
    • Efficient neural network acceleration ISA and architecture support
    Block Diagram -- Tensilica HiFi 1 DSP
  • Tensilica Vision Q7 DSP
    • Doubles Vision and AI Performance for Automotive, AR/VR, Mobile and Surveillance Markets
    Block Diagram -- Tensilica Vision Q7 DSP
  • NPU IP for Data Center and Automotive
    • 128-bit vector processing unit (shader + ext)
    • OpenCL 1.2 shader instruction set
    • Enhanced vision instruction set (EVIS)
    • INT 8/16/32b, Float 16/32b in PPU
    • Convolution layers
    Block Diagram -- NPU IP for Data Center and Automotive
  • NPU IP for AI Vision and AI Voice
    • 128-bit vector processing unit (shader + ext)
    • OpenCL 3.0 shader instruction set
    • Enhanced vision instruction set (EVIS)
    • INT 8/16/32b, Float 16/32b
    Block Diagram -- NPU IP for AI Vision and AI Voice
  • Low-power, low-gate-count, highly-configurable DSP core for audio and control processing
    • A comprehensive design environment and toolset
    • Very fast work-flow through the use of high-level front-end hierarchical Graphical Programming Environment, Core Synthesis and back-end “Tuning” tools
    Block Diagram -- Low-power, low-gate-count, highly-configurable DSP core for audio and control processing
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