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5G IP

5G IP cores ar support advanced wireless communication standards, including high-speed data transfer, low latency, and massive device connectivity, essential for 5G networks. They are ideal for a variety of applications, including mobile devices, IoT, automotive, and smart cities, enabling seamless, high-performance 5G experiences.

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Compare 70 5G IP from 28 vendors (1 - 10)
  • Polar Encoder / Decoder for 3GPP 5G NR
    • The patented polar encoding and decoding IP for the 3GPP New Radio uplink and downlink includes the entire processing chain, to provide quick and easy integration and minimize the amount of extra work needed.
    • The polar core uses PC- and CRC-aided SCL polar decoding techniques, in order to achieve compromise-free error correction performance.
    Block Diagram -- Polar Encoder / Decoder for 3GPP 5G NR
  • Ka-Band (24 - 33GHz) Zero-IF Transceiver
    • The ALTUS28TR is a highly integrated, mmWave, agile transceiver offering high performance and configurability for target applications in an advanced SiGe BiCMOS process technology.
    • This silicon intellectual property (SIP) delivers a versatile combination of high performance and low power consumption.
    Block Diagram -- Ka-Band (24 - 33GHz) Zero-IF Transceiver
  • NTN System Test Bench
    • Allows end-to-end testing of NB-IoT NTN system in lab environment.
    • supports 3GPP® Release 17 and 18 standards.
    • supports LEO transparent or regenerative modes of operation.
    • multiple-instancing and virtualisation to simulate UE community.
    Block Diagram -- NTN System Test Bench
  • NTN eNodeB System Test Bench
    • Allows end-to-end testing of NB-IoT NTN system in lab environment.
    • supports 3GPP® Release 17 and 18 standards.
    • supports LEO transparent or regenerative modes of operation.
    • multiple-instancing and virtualisation to simulate UE community.
    Block Diagram -- NTN eNodeB System Test Bench
  • Centralised Real Time Processor IP Core
    • CryptOne programmed algorithms:
    • Constant time modular exponentiation
    • Constant time, parallel modular exponentiation CRT
    • Constant time ECDSA sign/verify
    Block Diagram -- Centralised Real Time Processor IP Core
  • LDPC Encoder / Decoder for 3GPP 5G NR
    • The LDPC decoder product suite has been specifically designed as flexible IP to address the unique challenges of 5G NR across all use cases covered by the current standards, deliver market leading performance and efficiency, and be easily integrated into designs.
    Block Diagram -- LDPC Encoder / Decoder for 3GPP 5G NR
  • Hardware Security Module
    • GRHSM is an isolated system-on-chip (SoC) that can be used as a subsystem in a larger SoC design to implement a hardware security module or otherwise provide security functions to the larger system.
    • Use cases include crypto key storage, boot authentication, supervision, and offloading of cryptographic functions.
    Block Diagram -- Hardware Security Module
  • Blockchain Hardware Accelerator
    • Wide variety of ECC curves supported (Weierstrass, Edwards, Montgomery, Twisted-Edwards, …)
    • Ideal for FPGA/ASIC integration
    Block Diagram -- Blockchain Hardware Accelerator
  • Hardware Security Module (HSM) for Automotive
    • Secure key provisioning
    • Secure key storage
    • Secure counter
    • Flexible anti-tampering
    Block Diagram -- Hardware Security Module (HSM) for Automotive
  • Intrusion Detection System (IDS)
    • Part of a global threat detection, analysis and response solution form Chip-to-Cloud relying on Securyzr™ iSSP (integrated Security Services Platform).
    • Compliance with standard and Regulation.
    Block Diagram -- Intrusion Detection System (IDS)
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Semiconductor IP