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eFPGA IP

Welcome to the ultimate eFPGA IP hub! Explore our vast directory of eFPGA IP.

An eFPGA IP enables hardware re-programmability so that SoC/ASIC developers can make software/hardware trade-offs to optimize the platform bandwidth/power curve for various applications.

An eFPGA (embedded FPGA) is an IP core that is embedded within a custom ASIC or SoC. The IP can be licensed for use similar to that of other IP used in semiconductor designs. Unlike a standalone FPGA, eFPGA IP designers can select the exact amount of logic, DSP (or MLP) and memory resources required for their application. An eFPGA instance can also be used when flexibility is needed while lowering system cost, power and board space by eliminating the excess features of the standalone FPGA which are not required when moving into high-volume production.

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Compare 8 eFPGA IP from 5 vendors (1 - 8)
  • eFPGA IP - 100% third party standard cells
    • Every element of the eFPGA can be defined in numbers: logic cells, adaptive DSP (with and without FIR engine, add & mult size, amount), RAM (type and amount) and IOs.
    • In addition, Menta eFPGA IP Cores being 100% standard cells based, multiple power / performances trade-off can be achieved based on customer requirements.
    • The eFPGA IP Cores are provided as hard IPs (GDSII).
    • Menta eFPGA IP Cores use standard cells, and as such integrate smoothly into any standard ASIC design flow. Designers use RTL as the input to our software Origami Programmer to generate the eFPGA program file (bitstream) and obtain accurate performance evaluation.
    Block Diagram -- eFPGA IP - 100% third party standard cells
  • eFPGA
    • Customize Vega to suit your needs
    • Accelerate your processor with Vega eFPGA
    • Seamlessly integrate and verify Vega IP into your SoC design
    • Enhance flexibility with on-chip FPGA functionality
    Block Diagram -- eFPGA
  • eFPGA Hard IP Generator
    • Combination of over 30 years of programmable logic experience and expertise with proven standard ASIC design methodologies to create an eFPGA IP generator that can create and deliver a domain-specific eFPGA IP in as little as four weeks.
    Block Diagram -- eFPGA Hard IP Generator
  • Embedded FPGA
    • 75% lower power
    • 90% lower cost
    • 100× lower latency
    Block Diagram -- Embedded FPGA
  • Embedded FPGA
    • Fully integrated into RTL SOC design flow
    • Highly scalable and customizable
    • Technology independent
    Block Diagram -- Embedded FPGA
  • eFPGA IP as a synthesizable RTL core
    • Support of any technology node, foundry and process option
    • High LUTs density
    • Support of any kind of arithmetic block right within the IP
  • Radiation-Hardened eFPGA
    • Radiation-Hardened by Design (RHBD): Built to operate in space and defense applications, ensuring reliability under extreme conditions.
    • Customizable eFPGA IP: Tailored to specific mission requirements with adaptability to various process nodes and foundries.
    • High Reliability: Designed to withstand Total Ionizing Dose (TID) and Single Event Effects (SEE).
  • soft eFPGA IP
    • Please refer to the latest datasheet.
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Semiconductor IP