Memory Controller/PHY IP

Memory Interface IP cores support a wide range of memory types and standards, including DDR IP (Double Data Rate), GDDR IP (Graphics Double Data Rate), HBM IP (High Bandwidth Memory), and LPDDR IP (Low Power DDR), ensuring optimal performance in applications such as gaming, data centers, and mobile devices. NVM Express IP offers high-speed, low-latency storage interface for solid-state drives, while ONFI IP supports NAND flash memory communication. Additionally, SAS IP (Serial Attached SCSI) and SATA IP (Serial ATA) enable reliable, high-performance storage solutions, and SD/eMMC IP cores facilitate efficient data transfer for embedded systems.

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Compare 1,226 Memory Controller/PHY IP from 79 vendors (1 - 10)
  • Fault Tolerant DDR2/DDR3/DDR4 Memory controller
    • FTADDR is a memory controller for DDR2,DDR3 and DDR4 SDRAM memory devices.
    • It uses a strong error correction code to achieve exceptional fault tolerance
    Block Diagram -- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
  • Samsung 8LPU 3.3V SD/eMMC PHY
    • Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
    • Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
    • It includes an optional digi logic circuitry which is required for high-speed operations
    • It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards
    Block Diagram -- Samsung 8LPU 3.3V SD/eMMC PHY
  • GF 22FDX 1.8V/3.3V SD/eMMC PHY AG2 Platform
    • Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
    • Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
    • It includes an optional digi logic circuitry which is required for high-speed operations
    • It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards
    Block Diagram -- GF 22FDX 1.8V/3.3V SD/eMMC PHY AG2 Platform
  • Intel 16 SD/eMMC PHY North/South Poly Orientation
    • Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
    • Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
    • It includes an optional digi logic circuitry which is required for high-speed operations
    • It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards
    Block Diagram -- Intel 16 SD/eMMC PHY North/South Poly Orientation
  • TSMC 22ULL 1.8V/3.3V SD/eMMC PHY AG2
    • Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
    • Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
    • It includes an optional digi logic circuitry which is required for high-speed operations
    • It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards
    Block Diagram -- TSMC 22ULL 1.8V/3.3V SD/eMMC PHY AG2
  • TSMC N3E SD/eMMC PHY North/South Poly Orientation
    • Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
    • Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
    • It includes an optional digi logic circuitry which is required for high-speed operations
    • It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards
    Block Diagram -- TSMC N3E SD/eMMC PHY North/South Poly Orientation
  • TSMC N3P SD/eMMC PHY North/South Poly Orientation
    • Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
    • Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
    • It includes an optional digi logic circuitry which is required for high-speed operations
    • It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards
    Block Diagram -- TSMC N3P SD/eMMC PHY North/South Poly Orientation
  • AGILEX 7 R-Tile Gen5 NVMe Host IP
    • The LDS NVME HOST IP has been done for beginners and expert in NVMe to drive NVMe PCIe SSD.
    • The register file interface simplify the management of the IP for CPU interface or State Machine interface using Avalon bus.
    Block Diagram -- AGILEX 7 R-Tile Gen5 NVMe Host IP
  • NVME Host Zynq IP
    • PCIe RP and EP register configuration is done automatically.
    • NVMe register configuration is done automatically.
    • Able to manage 8 Name Spaces.
    • Able to manage until 16 IO Queue to fit specific user requirement.  Each IO Queue is independent.
    Block Diagram -- NVME Host Zynq  IP
  • NVME Host Kintex IP
    • PCIe RP and EP register configuration is done automatically.
    • NVMe register configuration is done automatically.
    • Able to manage 8 Name Spaces.
    • Able to manage until 16 IO Queue to fit specific user requirement.  Each IO Queue is independent.
    Block Diagram -- NVME Host Kintex IP
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