IP Catalog > Interface IP > Memory Controller/PHY IP

Memory Controller/PHY IP

Memory Interface IP cores support a wide range of memory types and standards, including DDR IP (Double Data Rate), GDDR IP (Graphics Double Data Rate), HBM IP (High Bandwidth Memory), and LPDDR IP (Low Power DDR), ensuring optimal performance in applications such as gaming, data centers, and mobile devices. NVM Express IP offers high-speed, low-latency storage interface for solid-state drives, while ONFI IP supports NAND flash memory communication. Additionally, SAS IP (Serial Attached SCSI) and SATA IP (Serial ATA) enable reliable, high-performance storage solutions, and SD/eMMC IP cores facilitate efficient data transfer for embedded systems.

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Search (1,358)
Compare 1,358 Memory Controller/PHY IP from 81 vendors (1 - 10)
  • PSRAM/RPC PHY & Controller
    • The DDR IP Mixed-Signal MR PSRAM PHY and RPC PHY provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible PSRAM/RPC devices
    • It is optimized for low-power and high-speed applications with robust timing and small silicon area
    • The PSRAM PHY supports AP memory UHS/OPI PSRAM components on the market, and the RPC PHY supports ETRON components on the market
    Block Diagram -- PSRAM/RPC PHY & Controller
  • ONFI PHY & Controller
    • The ONFI IP provides Turnkey solutions for IC requiring access to ONFI-compatible NAND Flash devices
    • Optimized for low power and high-speed applications, it features robust timing and a compact silicon area
    • It supports all ONFI NAND Flash components available on the market
    Block Diagram -- ONFI PHY & Controller
  • MRDIMM DDR5 & DDR5/4 PHY & Controller
    • The DDR IP Mixed-Signal MRDIMM DDR5 PHY and DDR5/4 Combo PHY provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM or MRDIMM/ RDIMM/ LRDIMM/ UDIMM DDR5 devices
    • It is optimized for low-power and high-speed applications with robust timing and small silicon area
    • It supports all JEDEC DDR5/4 SDRAM components in the market
    Block Diagram -- MRDIMM DDR5 & DDR5/4 PHY & Controller
  • LPDDR5X/5/4X/4 PHY & Controller
    • The DDR IP Mixed-Signal LPDDR5X/5/4X/4 Combo PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices
    • It is optimized for low-power and high-speed applications with robust timing and small silicon area
    • It supports all JEDEC LPDDR5X/5/4X/4 SDRAM components in the market
    • The PHY components contain DDR-specialized functional and utility high-performance I/Os, critical timing synchronization modules (TSM), and low power/jitter DLLs with programmable fine-grain control for any SDRAM interface
    Block Diagram -- LPDDR5X/5/4X/4 PHY & Controller
  • HBM4/3E Combo PHY & Controller
    • The fourth-generation and third-generation HBM (HBM4/3E) technology is outlined by the JESD238A standard (for HBM3E) and an upcoming specification (for HBM4)
    • These technologies feature 256-bit memory access per channel, with a 1024-bit input/output interface for HBM3E and up to a 2048-bit interface for HBM4
    Block Diagram -- HBM4/3E Combo PHY & Controller
  • GDDR7 PHY & Controller
    • The GDDR7 PHY is fully compliant with the JEDEC GDDR7 standard, supporting data rates of up to 32 Gbps in PAM3 mode
    • In PAM3 mode, each byte consists of ten DQ signals and one DQE signal, while the GDDR7 also supports NRZ I/O signaling for low-power operation
    • With a maximum speed of 32 Gbps per pin, The GDDR7 PHY delivers a peak bandwidth of up to 128 GB/s per memory device
    Block Diagram -- GDDR7 PHY & Controller
  • GDDR6X/6 Combo PHY & Controller
    • The GDDR6X/6 PHY is fully compliant with the JEDEC GDDR6X/6 standard, supporting data rates of up to 20Gbps per pin for PAM2 GDDR6 mode and 24Gbps for PAM4 GDDR6X mode
    • The GDDR6X/6 interface supports 2 channels, each with 16 bits for a total data width of 32 bits per memory device
    • With a maximum speed of 20/24Gbps per pin, The GDDR6X/6 Combo PHY delivers a peak bandwidth of up to 80GB/s or 96GB/s per memory device
    Block Diagram -- GDDR6X/6 Combo PHY & Controller
  • eMMC/SD/SDIO Combo IP
    • The eMMC/SD/SDIO Combo IP is a comprehensive solution designed to support high-performance storage and I/O connectivity for a wide range of applications
    • This IP integrates a host controller and PHY, enabling seamless communication with eMMC, SD, and SDIO devices
    • When connecting the SD/SDIO device, the IP supports DS, HS, SDR12, SDR25, SDR50, SDR104, and DDR50 speed modes
    Block Diagram -- eMMC/SD/SDIO Combo IP
  • GDDR6 PHY IP for 12nm
    • JEDEC JESD250 compliant GDDR6 support
    • X16 mode, X8 mode, and pseudo-channel mode
    • Low frequency RDQS mode support
    Block Diagram -- GDDR6 PHY IP for 12nm
  • LPDDR5X/5/4X/4 combo PHY at 12nm
    • Compliant with JEDEC JESD209-5C for LPDDR5x/5/4x/4 with PHY standards
    • Delivering up to 8533Mbps
    • DFI 5.1 specification PHY Interface Compliant
    • Support up to 4 ranks
    • Multiple frequency states
    Block Diagram -- LPDDR5X/5/4X/4 combo PHY at 12nm
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