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Universal Timers System
- The Universal Timers System is a programmable and highly configurable device that comprises seven submodules: Pulse Width Modulation (PWM), Timer 1, Timer 2, Timer 3, Real-Time Interrupt (RTI), Computer Operates Properly (COP), Pulse Accumulator (PA)
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8b/10b Encoder/Decoder
- The CODEC_8B10B IP Core is a scalable 8B/10B Encoder/Decoder pair suitable for a wide range of serial data transmission applications.
- The design is optimized for very high-speed operation and is suitable for use in serial data links of 6 GHz+ on basic FPGA devices.
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Register, Configuration and Control Bus
- A2R provides an interconnection mechanism between control registers in an ASIC design and any number of control devices; CPUs, debug ports etc..
- The bus is especially suited for synthesizable designs. It is specifically developed to meet the challenges of long interconnect delays in large System-on-chip designs and can be tailored to match system clock rates.
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Quad SPI Controller
- Configurable SPI modes
- Supports programmable SPI clocking modes
- Programmable interrupt on SPI-done
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Real-Time Clock with APB Interface
- The RTC-APB core implements a real-time clock (RTC) and calendar facility together with an alarm function.
- To keep track of time of day the core uses a series Binary-Coded Decimal (BCD) counters that count time and date with an accuracy of 1/10 of s second.
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MPEG Transport Stream Multiplexing & Encapsulation Engine
- The MTS-E core multiplexes and encapsulates audio, video, and metadata streams in a single MPEG Transport Stream (MTS), and optionally encapsulates the TS packets in Real-Time Transport Protocol (RTP) packets.
- Under its default configuration, the MTS-E multiplexing and encapsulation engine supports two input stream channels, e.g., one Audio and one Video.
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Timer/Counter with APB Interface
- 32-bit Timer/Counter
- 32-bit APB3 interface
- Independent APB and timer clocks
- Programmable prescaler (synthesis-time defined bit-width)
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Watchdog Timer with APB Interface
- Programmable 32-bit Down Counter with 16-bit pre-scaler
- Interrupt generation on counter timeout
- Reset generation on counter timeout in case that interrupt was not serviced
- Locking mechanism to prevent non-intentional configuration
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WATCHDOG IIP
- Supports to prevent system lock up due to software anomalies or hardware failure
- Supports cold reset after configured interval
- Supports interrupt indication after programmed time period
- Supports both firmware and hardware pause and resume
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TIMER IIP
- Supports 32 timers each of 32 bit.
- Supports up/down counting modes.
- Supports configurable counter width.
- Supports to count a maximum value of 32'hFFFFFFFF in Generate and Capture mode.
