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Other
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Quad SPI Controller
- Configurable SPI modes
- Supports programmable SPI clocking modes
- Programmable interrupt on SPI-done
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Path tracing/Ray tracing accelerator
- Powerful Path Tracing Acceleration GPU IP Solution
- ‘Unified’ Traversal and Intersection Test
- Based on High Performance MIMD Architecture
- Highly Applicable for Servers and High End GPU Chips
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Hardware NLM (Non-Local-Mean) Video Noise Reduction IP core
- parameterized search-window size
- parameterized number of bits per pixel
- efficient implementation
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AXI Fabric Package for Scalable SoC Applications
- AE300FB – AXI Fabric
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MPEG Transport Stream Multiplexing & Encapsulation Engine
- MPEG Transport Stream Multiplexing & Encapsulation
- RTP Encapsulation
- Easy Integration
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AHB Cache Controller Core
- Adds single or multilevel cache memory to originally cache-less deeply embedded processors, DSPs, or ASIPs.
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AXI4 Memory-Mapped to/from AXI4-Stream DMA
- Independent AXI4 compliant single channel modules
- AXI4-Lite port for access to control and status registers
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Spatial image transformation accelerator
- Streaming is compatible with AXI-Stream protocol
- Transformation and image dimension parameters are configurable through AXI4-Lite
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Stream Buffer Controller
- The IP Core supports four different operation modes for each channel:
- Supports up to 16 write and read streams (depending on product options)
- Configurable status flags for write and read path
- Vendor-independent implementation
