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Search (14)
Compare 14 Other from 8 vendors (1 - 10)
  • ATSC 8-VSB modulator
    • The CMS0033 ATSC 8-VSB Modulator with integrated Channel Coder has been designed specifically to implement the 8-VSB requirements of the ATSC Digital Television Standard (A/53).
    • The core provides all the necessary processing steps to modulate a single transport stream into a complex I/Q signal for input to a pair of DACs, or a DDS up-conversion DAC such as the AD9857(or AD9957). Optionally, the output can be selected as an IF to supply a signal DAC.
    Block Diagram -- ATSC 8-VSB modulator
  • GSM GPRS EDGE Protocol Stack SW IP
    • Class B implementation multi-slot class 12 to 3GPP Release 1999 June 2007
    • GPRS PDP context. Packet services accessed via integrated TCP/ IP stack, or via PPP using an external PC or PDA.
    • Conforms to 3GPP Release ’99 / GCF-CC v3.35 bis (GCF-CC Version 3.35.0 dated 2009-07-06) and NAPRD.03 v5.0 bis (PTCRB NAPRD.03 v5.0) based on STAR-Let200Q M2M platform
    • Data rates to 80Kbps (GPRS); 400Kbps (EGPRS)
    Block Diagram -- GSM GPRS EDGE Protocol Stack SW IP
  • 802.15.4 (Zigbee, 6LoWPAN, RF4CE, ISM) PHY
    • Fully Integrated 802.15.4 Transceiver
    • High Performance
    • Low Power Consumption
    Block Diagram -- 802.15.4 (Zigbee, 6LoWPAN, RF4CE, ISM) PHY
  • Mobile Phase Recovering Equalizer
    • 17-tap complex-arithmetic LMS Channel Equalizer with adaptation bandwidth and leakage rate control as well as independent coefficient hold and reset controls
    • VV4 Quasi-Coherent Demodulator for signal phase recovery and differential detection
    • Integrated Symbol Slicer provides demodulated soft-decision outputs
    • AGC output controls in proportional and up/dn format for constant-modulus and phase-locked processing
    Block Diagram -- Mobile Phase Recovering Equalizer
  • Maximum normalised correlation core
    • Sliding window energy estimator on IQ input samples
    • Sliding window energy estimator on lagged IQ input samples
    • Sliding autocorrelation between the IQ input and lagged IQ input samples.
    • Detection threshold for |ACF| > energy
  • Wideband Digital Down Converter (Digital DDC)
    • Fully synchronous design, using single clock
    • Fully synthesizable drop-in module for FPGAs
    • Optimized for high performance and low resources
    • Low implementation loss
  • RS-QPSK Modem with low latency
    • Fully synchronous design, using single clock
    • Fully synthesizable drop-in module for FPGAs
    • Optimized for high performance and low resources
    • Low implementation loss
  • PSK Demodulator
    • Fully synchronous design
    • Fully synthesizable
    • Optimized for high performance and low resources
    • Low implementation loss
  • Multi-gigabit Modem for E-band backhaul systems
    • Fully synchronous design, using single clock
    • Fully synthesizable drop-in module for FPGAs
    • Optimized for high performance and low resources
    • Low implementation loss
  • Burst-mode BPSK Modem with highly efficient packet structure
    • Fully synchronous design, using single clock
    • Fully synthesizable drop-in module for FPGAs
    • Optimized for high performance and low resources
    • Low implementation loss
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