DSP & Math IP
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DSP & Math IP
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LDPC Decoder for 5G NR and Wireless
- The 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance.
- It employs the Min-Sum LDPC decoding algorithm to ensure efficient decoding.
- The core allows for programmable internal bit widths at compile time, though the default values are usually sufficient.
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LDPC Encoder/Decoder (LDPC)
- Supporting a wide range of data-rates
- 50MB/s to 4.0GB/s for a single LDPC instance
- Scalable platform provides the basis for customer specific custom-LDPC cores
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eMMC LDPC Encoder/Decoder
- Supports data rates from 50 MB/s to 9.0 GB/s.
- Enables custom LDPC core development for specific requirements.
- Wide range of codeword sizes.
- Maximum supported parity.
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APB Pulse Width Modulator
- The APB PWM Module is a standard APB peripheral that generates a programmable duty cycle output signal.
- The frequency of the output waveform is either PCLK/256 or PCLK/4096, depending on whether a 4-bit prescaler is enabled.
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Radar processing IP suite for Advanced Driver Assistance Systems
- The eSi-ADAS™ is a suite of radar accelerator IP including a complete Radar co-processor engine, they enhance the overall performance and capabilities of radar systems for automotive, drone and UAV applications that require fast and responsive situational awareness.
- The IP has been licensed to some of the leading automotive Tier 1 and Tier 2 suppliers and is in production vehicles.
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VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
- VESA DisplayPort 1.4 compliant
- Reed-Solomon RS (254,250) FEC, 10-bit symbols
- Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
- DisplayPort main 8b/10b encoder included (Tx only)
- Status and control can be done with signals or optionally via an integrated APB register module (Rx)
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Reed Solomon FEC
- Designed to support any Reed Solomon code.
- Custom tailored to support specific codes see standard table below
- Low Latency
- FEC Processing cycles optimized for reduced buffering
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RGB to ITU-R 601/656 Encoder
- The DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller (or any LCD display timing & control unit) to a TFT LCD Panel by-way-of a CCIR 601 / CCIR 656 interface.
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LDPC Encoder/Decoder IP Core
- IPM-LDPC for NandFlash Storage: Adaptable BER, Up to 6 checks per bit, customizable data path
- IPM-LDPC for short code: option to be full asynchronous, option to be in 3 clock cycles
- fully configurable: matrix generator, data path, number of iteration checks, packet size
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Power-On Reset - Flexible Threshold (1-1.3V), Ultra Low Current (100nA) - SilTerra 0.16µm CL160G
- This macro-cell is an ultra low consumption Power-On Reset (POR) core designed for SilTerra 0.16μm CL160G CMOS technology.
- The threshold sensing voltage can be configured from 1V to 1.3V (default is 1.15V). A hysteresis of 120mV is added to avoid false reset glitches in noisy supplies.
