DSP & Math IP

The A2FD is a fully synthesizable module implemented in Verilog RTL.
It is a co-processor unit providing floating-point computation compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic (IEEE Standard).
It is designed to provide high performance floating-point computation while minimizing die size and power. Pipelined, single-cycle throughput operation is available for all operations except Divide, Remainder and Square Root operations.

The A2FM product is a collection of floating-point execution units compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic (IEEE-754 Standard).
The units are designed for high frequency, high throughput implementations. Each unit is implemented as a state less pipeline that can easily be integrated into a high-performance processor design.

The sFIFO controls are designed to operate over a wide range of clock frequencies.
The interface signals are fully synchronous; no asynchronous signals are present on either side. Only reset may be asynchronous in that it may be asserted asynchronously and synchronized internally to the clock.

The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
A parameter defines the ratio of the input width to the output width.
For example, if the input width is 32-bits and the Reduction Factor is 4 the the output width is 8-bits.

The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
A parameter defines the ratio of the input width to the output width.
For example, if the input width is 8-bits and the Expansion Factor is 4 the the output width is 32-bits.

The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
The interface is fully compatible with a Standard FIFO interface and they may be mixed and matched.
A “Stall” may be generated by gating the POP and ORDY signals to arrest the normal flow of data down the pipeline and allows any given stage to take multiple cycles when necessary.

The A2FH is a co-processor unit providing floating-point computation compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic (IEEE-754R Standard).
It is designed to provide a powerful floating-point functionality for low-power, low frequency applications.

The A2F is a fully synthesizable module implemented in Verilog RTL.
It is a co-processor unit providing floating-point computation compliant with the ANSI/IEEE Std 754-1985, IEEE Standard for Binary Floating-Point Arithmetic (IEEE Standard).
It is designed to provide high performance floating-point computation while minimizing die size and power.

Supports 32/64/128/256/512-point complex FFT and IFFT and can switch dynamically
Inputs and outputs data in the natural order
Throughput of 1 sample (In-phase I + quadrature Q) per 4 clocks; no-gap processing of the input data
Parameterized bit width.

The FFT4T core implements a 128 point complex FFT and IFFT over 12 data streams in hardware. It runs at the clock frequency four times higher than the insput sampling frequency.
FFT4T core is a specialized FFT/IFFT processor intended for a situation where an RF signal is recieved over multiple channels in parallel and its filtering is to be performed in the frequency domain. The core fits nicely into, for example, a multichannel GPS system.