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Compare 826 DSP & Math IP from 105 vendors (1 - 10)
  • DVB-S2-LDPC-BCH
    • Irregular parity check matrix
    • Layered decoding
    • Minimum sum algorithm
    • Soft decision decoding
    • BCH decoder works on GF (2m) where m=16 or 14 and corrects up to t errors, where t = 8, 10 or 12
    Block Diagram -- DVB-S2-LDPC-BCH
  • ASIP-1 FFT Engine
    • Platform to design Application Specific Instruction Set Processors (ASIPs).
    • Ideal for supporting multi-standard systems.
    • Supports a wide range of complex DSP functions.
    Block Diagram -- ASIP-1 FFT Engine
  • ASIP-2 Programmable Filter Engine
    • Platform to design Application Specific Instruction Set Processors (ASIPs).
    • Ideal for supporting multi-standard systems.
    • Supports a wide range of complex DSP functions
    • The ASIP2 performs Fast Fourier Transform (FFT) to convert time domain signals to frequency domain signals for further processing. It supports FFT sizes from 4 to 8K.
    Block Diagram -- ASIP-2 Programmable Filter Engine
  • MIMO Decoder
    • Includes QR Decomposition, Dynamic scale and  K-best Decoder
    • Fixed Depth K-Best Decoder (K=16)
    • Achieves close-to ML BER performance
    • Supports synchronized streams with different QAM (from BPSK to 64 QAM) dependent on MIMO mode
    • Supports square and non-square QAM
    Block Diagram -- MIMO Decoder
  • MIMO Sphere Decoder
    • Fixed Complexity Sphere Decoder providing fixed throughput
    • Achieves close-to ML BER performance
    • MATLAB and C model for – MIMO 2×2 and 4×4 – Can be modified to support other MIMO sizes – BPSK, 4-QAM, 16-QAM and 64-QAM
    • Efficient and optimized FPGA Architecture (4×4 MIMO, 16-QAM)
    Block Diagram -- MIMO Sphere Decoder
  • BCH Decoder
    • BCH decoder compliant with the DVB-T2/S2 standard.
    • Available for Altera/Xilinx FPGA or ASIC implementation.
    • High speed design.
    • BCH decoder works on GF(2M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
    • Area and power optimized implementation.
    Block Diagram -- BCH Decoder
  • LDPC Decoder IS-GPS-800D
    • Irregular parity check matrix
    • Layered Decoding
    • Minimum sum algorithm
    • Configurable number of iterations
    • Soft decision decoding
    Block Diagram -- LDPC Decoder IS-GPS-800D
  • Reed Solomon
    • High performance Reed Solomon IP Core (Encoder and Decoder).
    • Supports error and erasure decoding.
    • Parameterized codeword length.
    • Code generator polynomial: (x + λ^0 )(x + λ^1 )(x + λ^2 )...(x + λ^15 ).
    Block Diagram -- Reed Solomon
  • Viterbi Decoder
    • Supports 1/N coderates
    • Configurable constraint length
    • Configurable generator polynomials
    • Configurable precision of state metrics
    Block Diagram -- Viterbi Decoder
  • DVB-T2 Demodulator
    • This design is a DVB-T2 OFDM demodulator, supplied as portable and synthesizable Verilog-2001 IP.
    • The system was designed to be used in conjunction with a standard RF tuner.
    • QAM signal constellations are supported, including QAM16, QAM64 and QAM256 . QPSK, and BPSK also supported. 
    Block Diagram -- DVB-T2 Demodulator
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