MIPI IP
MIPI IP cores enable seamless communication between processors, sensors, and peripherals in mobile, automotive, and consumer electronics applications. Two key components of MIPI IP cores are the MIPI Controller IP and MIPI PHY IP. The MIPI Controller IP manages the data transfer process, ensuring efficient and reliable communication between devices, while the MIPI PHY IP handles the physical layer of the interface, ensuring high-speed, noise-resistant signal transmission.
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MIPI IP
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MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI C-PHY/D-PHY Combo RX+ IP 4.5Gsps/4.5Gbps in TSMC N5
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
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MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for C-PHY specification Version 1.2
- Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
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MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
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MIPI DSI Transmit Controller v1.3
- Compliant with the following MIPI specifications
- DSI Host-side (display module) interface supports
- Application Processor Connectivity and video/command processing
- AHB Interface for register configuration and monitoring using programmed IO
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MIPI DSI Receiver Controller v1.3
- Compliant with the following MIPI specifications
- DSI Host-side interface supports
- Display Panel Connectivity and video/command processing
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MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI for C-PHY specification Version 1.2
- Compliant to MIPI for D-PHY specification Version 1.2
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I3C Host Controller
- Compliant with MIPI I3C Specification V1.0
- Supports up to 12.5 MHz operation using Push-Pull.
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MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
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MIPI DSI-2 Controller Core
- Fully MIPI DSI-2/DSI standard compliant
- 64 and 32-bit core widths
- Host (Tx) and Peripheral (Rx) versions
- Supports 1-4, 9.0+ Gbps D-PHY data lanes
- Supports 1-4, 6.0+ Gsym/s C-PHY lane (trio)
- Supports all data types
