MIPI IP
Welcome to the ultimate MIPI IP hub! Explore our vast directory of MIPI IP.
MIPI, which stands for Mobile Industry Processor Interface, is an industry-driven standard aimed at simplifying the integration of different advanced technologies into small form factor devices while ensuring optimal communication efficiency and power consumption.
MIPI IP cores in this category include MIPI D-PHY, C-PHY, and M-PHY, among others.
All offers in
MIPI IP
Filter
Compare
502
MIPI IP
from 43 vendors
(1
-
10)
-
MIPI C-PHY/D-PHY Combo CSI-2 RX+ IP (6.0Gsps/trio, 4.5Gbps/lane) in TSMC N6
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
-
MIPI C-PHY/D-PHY Combo RX+ IP 4.5Gsps/4.5Gbps in TSMC N5
- Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
-
MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for C-PHY specification Version 1.2
- Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
-
MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
-
MIPI DSI Transmit Controller v1.3
- Compliant with the following MIPI specifications
- DSI Host-side (display module) interface supports
- Application Processor Connectivity and video/command processing
- AHB Interface for register configuration and monitoring using programmed IO
-
MIPI DSI Receiver Controller v1.3
- Compliant with the following MIPI specifications
- DSI Host-side interface supports
- Display Panel Connectivity and video/command processing
-
MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI for C-PHY specification Version 1.2
- Compliant to MIPI for D-PHY specification Version 1.2
-
I3C Host Controller
- Compliant with MIPI I3C Specification V1.0
- Supports up to 12.5 MHz operation using Push-Pull.
-
MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
-
MIPI CSI-2 Controller Core V2
- Fully CSI-2 standard compliant
- 64 and 32 bit core widths
- Transmit and Receive versions
